/********************************************************************
* Copyright (C) 2011-2018 Texas Instruments Incorporated.
 * 
 *  Redistribution and use in source and binary forms, with or without 
 *  modification, are permitted provided that the following conditions 
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright 
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the 
 *    documentation and/or other materials provided with the   
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/
/*********************************************************************
* file: cslr_bootcfg.h
*
* Brief: This file contains the Register Description for TCI6634 bootcfg
*
*********************************************************************/
#ifndef CSLR_BOOTCFG_V0_H
#define CSLR_BOOTCFG_V0_H

/* CSL Modification:
 *  The file has been modified from the AUTOGEN file for the following
 *  reasons:-
 *      a) Header files are included as per RTSC guidelines
 *      b) Changed BOOTADDR_GEM0_REG-BOOTADDR_GEM7_REG to an array BOOTADDR_GEM_REG[8]
 *      c) Changed RSTMUX0-RSTMUX11 to an array RSTMUX[12]
 *      d) Changed NMIGR_0-NMIGR_7 to an array NMIGR[8]
 *      e) Changed IPCGR0-IPCGR11 to an array IPCGR[12]
 *      f) Changed IPCAR0-IPCAR11 to an array IPCAR[12]
 *      g) Updated main/pa/ddr3a/ddr3b/arm PLLC definitions
 */

#include <ti/csl/cslr.h>
#include <ti/csl/tistdtypes.h>


#ifdef __cplusplus
extern "C" {
#endif

/* Minimum unit = 1 byte */

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    volatile Uint32 REVISION_REG;
    volatile Uint8 RSVD0[4];
    volatile Uint32 DIE_ID_REG0;
    volatile Uint32 DIE_ID_REG1;
    volatile Uint32 DIE_ID_REG2;
    volatile Uint32 DIE_ID_REG3;
    volatile Uint32 JTAG_ID_REG0;
    volatile Uint32 JTAG_ID_REG1;
    volatile Uint32 DEVSTAT;
    volatile Uint8 RSVD1[20];
    volatile Uint32 KICK_REG0;
    volatile Uint32 KICK_REG1;
#ifdef CSL_MODIFICATION
    volatile Uint32 BOOTADDR_GEM0_REG;
    volatile Uint32 BOOTADDR_GEM1_REG;
    volatile Uint32 BOOTADDR_GEM2_REG;
    volatile Uint32 BOOTADDR_GEM3_REG;
    volatile Uint32 BOOTADDR_GEM4_REG;
    volatile Uint32 BOOTADDR_GEM5_REG;
    volatile Uint32 BOOTADDR_GEM6_REG;
    volatile Uint32 BOOTADDR_GEM7_REG;
#else
    volatile Uint32 BOOTADDR_GEM_REG[8];
#endif
    volatile Uint8 RSVD2[128];
    volatile Uint32 INTR_RAW_STATUS_REG; /* This gives the raw interrupt status for reads and allows setting of interrupts for writes */
    volatile Uint32 INTR_ENABLED_STATUS_REG; /* This gives the enabled interrupt status for reads and allows clearing of interrupts for writes */
    volatile Uint32 INTR_ENABLE_REG; /* Contains the interrupt enables on reads and allows setting on writes */
    volatile Uint32 INTR_ENABLE_CLR_REG; /* Contains the interrupt enables on reads and allows clearing on writes */
    volatile Uint32 EOI_REG; /* The End of Interrupt write declares a serviced interrupt */
    volatile Uint32 FAULT_ADDRESS_REG; /* This holds the address of the reported fault */
    volatile Uint32 FAULT_STATUS_REG; /* This holds the parameters and status of a fault */
    volatile Uint32 FAULT_CLEAR_REG; /* This allows clearing of the current fault with a write of 1 */
    volatile Uint8 RSVD3[16];
    volatile Uint32 MAC_ID0;
    volatile Uint32 MAC_ID1;
    volatile Uint8 RSVD4[16];
    volatile Uint32 PCIEVENDORID;
    volatile Uint32 DISABLESTAT;
    volatile Uint32 LRSTNMISTAT_CLR;
    volatile Uint32 RESET_STAT_CLR;
    volatile Uint8 RSVD5[4];
    volatile Uint32 BOOT_COMPLETE;
    volatile Uint32 BOOT_PROGRESS;
    volatile Uint32 RESET_STAT;
    volatile Uint32 LRSTNMISTAT;
    volatile Uint32 DEVCFG;
    volatile Uint32 PWR_STAT;
    volatile Uint8 RSVD6[44];
    volatile Uint32 CLASS0_EFUSE0_REG;
    volatile Uint8 RSVD7[12];
    volatile Uint32 SEN0_0_EFUSE_REG0;
    volatile Uint32 SEN1_0_EFUSE_REG1;
    volatile Uint32 SEN2_0_EFUSE_REG2;
    volatile Uint32 SEN3_0_EFUSE_REG3;
    volatile Uint32 SEN0_1_EFUSE_REG4;
    volatile Uint32 SEN1_1_EFUSE_REG5;
    volatile Uint32 SEN2_1_EFUSE_REG6;
    volatile Uint32 SEN3_1_EFUSE_REG7;
    volatile Uint32 SEN0_2_EFUSE_REG8;
    volatile Uint32 SEN1_2_EFUSE_REG9;
    volatile Uint32 SEN2_2_EFUSE_REG10;
    volatile Uint32 SEN3_2_EFUSE_REG11;
    volatile Uint32 SEN0_3_EFUSE_REG12;
    volatile Uint32 SEN1_3_EFUSE_REG13;
    volatile Uint32 SEN2_3_EFUSE_REG14;
    volatile Uint32 SEN3_3_EFUSE_REG15;
    volatile Uint8 RSVD8[48];
#ifdef CSL_MODIFICATION
    volatile Uint32 NMIGR_0;
    volatile Uint32 NMIGR_1;
    volatile Uint32 NMIGR_2;
    volatile Uint32 NMIGR_3;
    volatile Uint32 NMIGR_4;
    volatile Uint32 NMIGR_5;
    volatile Uint32 NMIGR_6;
    volatile Uint32 NMIGR_7;
#else
    volatile Uint32 NMIGR[8];
#endif
    volatile Uint8 RSVD9[32];
#ifdef CSL_MODIFICATION
    volatile Uint32 IPCGR0;
    volatile Uint32 IPCGR1;
    volatile Uint32 IPCGR2;
    volatile Uint32 IPCGR3;
    volatile Uint32 IPCGR4;
    volatile Uint32 IPCGR5;
    volatile Uint32 IPCGR6;
    volatile Uint32 IPCGR7;
    volatile Uint32 IPCGR8;
    volatile Uint32 IPCGR9;
    volatile Uint32 IPCGR10;
    volatile Uint32 IPCGR11;
#else
    volatile Uint32 IPCGR[12];
#endif
    volatile Uint8 RSVD10[12];
    volatile Uint32 IPCGRH;
#ifdef CSL_MODIFICATION
    volatile Uint32 IPCAR0;
    volatile Uint32 IPCAR1;
    volatile Uint32 IPCAR2;
    volatile Uint32 IPCAR3;
    volatile Uint32 IPCAR4;
    volatile Uint32 IPCAR5;
    volatile Uint32 IPCAR6;
    volatile Uint32 IPCAR7;
    volatile Uint32 IPCAR8;
    volatile Uint32 IPCAR9;
    volatile Uint32 IPCAR10;
    volatile Uint32 IPCAR11;
#else
    volatile Uint32 IPCAR[12];
#endif
    volatile Uint8 RSVD11[12];
    volatile Uint32 IPCARH;
    volatile Uint8 RSVD12[60];
    volatile Uint32 TINPSEL_MSB;
    volatile Uint32 TINPSEL;
    volatile Uint32 TOUTSEL;
#ifdef CSL_MODIFICATION
    volatile Uint32 RSTMUX0;
    volatile Uint32 RSTMUX1;
    volatile Uint32 RSTMUX2;
    volatile Uint32 RSTMUX3;
    volatile Uint32 RSTMUX4;
    volatile Uint32 RSTMUX5;
    volatile Uint32 RSTMUX6;
    volatile Uint32 RSTMUX7;
    volatile Uint32 RSTMUX8;
    volatile Uint32 RSTMUX9;
    volatile Uint32 RSTMUX10;
    volatile Uint32 RSTMUX11;
#else
    volatile Uint32 RSTMUX[12];
#endif
    volatile Uint8 RSVD13[24];
    volatile Uint32 MAIN_PLL_CTL0;
    volatile Uint32 MAIN_PLL_CTL1;
    volatile Uint32 PASS_PLL_CTL0;
    volatile Uint32 PASS_PLL_CTL1;
    volatile Uint32 DDR3A_PLL_CTL0;
    volatile Uint32 DDR3A_PLL_CTL1;
    volatile Uint32 DDR3B_PLL_CTL0;
    volatile Uint32 DDR3B_PLL_CTL1;
    volatile Uint32 ARM_PLL_CTL0;
    volatile Uint32 ARM_PLL_CTL1;
    volatile Uint8 RSVD14[36];
    volatile Uint32 SECURE_CONTROL;
    volatile Uint8 RSVD15[96];
    volatile Uint32 ARM_ENDIAN_CFG0_0;
    volatile Uint32 ARM_ENDIAN_CFG0_1;
    volatile Uint32 ARM_ENDIAN_CFG0_2;
    volatile Uint8 RSVD16[4];
    volatile Uint32 ARM_ENDIAN_CFG1_0;
    volatile Uint32 ARM_ENDIAN_CFG1_1;
    volatile Uint32 ARM_ENDIAN_CFG1_2;
    volatile Uint8 RSVD17[4];
    volatile Uint32 ARM_ENDIAN_CFG2_0;
    volatile Uint32 ARM_ENDIAN_CFG2_1;
    volatile Uint32 ARM_ENDIAN_CFG2_2;
    volatile Uint8 RSVD18[4];
    volatile Uint32 ARM_ENDIAN_CFG3_0;
    volatile Uint32 ARM_ENDIAN_CFG3_1;
    volatile Uint32 ARM_ENDIAN_CFG3_2;
    volatile Uint8 RSVD19[4];
    volatile Uint32 ARM_ENDIAN_CFG4_0;
    volatile Uint32 ARM_ENDIAN_CFG4_1;
    volatile Uint32 ARM_ENDIAN_CFG4_2;
    volatile Uint8 RSVD20[4];
    volatile Uint32 ARM_ENDIAN_CFG5_0;
    volatile Uint32 ARM_ENDIAN_CFG5_1;
    volatile Uint32 ARM_ENDIAN_CFG5_2;
    volatile Uint8 RSVD21[4];
    volatile Uint32 ARM_ENDIAN_CFG6_0;
    volatile Uint32 ARM_ENDIAN_CFG6_1;
    volatile Uint32 ARM_ENDIAN_CFG6_2;
    volatile Uint8 RSVD22[4];
    volatile Uint32 ARM_ENDIAN_CFG7_0;
    volatile Uint32 ARM_ENDIAN_CFG7_1;
    volatile Uint32 ARM_ENDIAN_CFG7_2;
    volatile Uint8 RSVD23[388];
    volatile Uint32 CLASS0_EFUSE1_REG;
    volatile Uint8 RSVD24[12];
    volatile Uint32 EFUSE1_REG0;
    volatile Uint32 EFUSE1_REG1;
    volatile Uint32 EFUSE1_REG2;
    volatile Uint32 EFUSE1_REG3;
    volatile Uint32 EFUSE1_REG4;
    volatile Uint32 EFUSE1_REG5;
    volatile Uint32 EFUSE1_REG6;
    volatile Uint32 EFUSE1_REG7;
    volatile Uint32 EFUSE1_REG8;
    volatile Uint32 EFUSE1_REG9;
    volatile Uint32 EFUSE1_REG10;
    volatile Uint32 EFUSE1_REG11;
    volatile Uint32 EFUSE1_REG12;
    volatile Uint32 EFUSE1_REG13;
    volatile Uint32 EFUSE1_REG14;
    volatile Uint32 EFUSE1_REG15;
    volatile Uint8 RSVD25[176];
    volatile Uint32 CHIP_MISC;
    volatile Uint32 SR_PINCTL;
    volatile Uint32 SPARE0;
    volatile Uint32 SPARE1;
    volatile Uint32 SYS_ENDIAN;
    volatile Uint8 RSVD26[28];
    volatile Uint32 SYNCE_PINCTL;
    volatile Uint32 MARGIN3;
    volatile Uint32 USB_REG0;
    volatile Uint32 USB_REG1;
    volatile Uint32 USB_REG2;
    volatile Uint32 USB_REG3;
    volatile Uint32 USB_REG4;
    volatile Uint32 USB_REG5;
    volatile Uint32 USB_REG6;
    volatile Uint32 USB_REG7;
    volatile Uint8 RSVD27[1192];
    volatile Uint32 LED_CORE_PASSDONE0;
    volatile Uint32 LED_CORE_PASSDONE1;
    volatile Uint8 RSVD28[24];
    volatile Uint32 LED_ARM_BOOTADDR;
    volatile Uint8 RSVD29[12];
    volatile Uint32 LED_GPIO_CLR;
    volatile Uint32 LED_GPIO_CLR1;
    volatile Uint32 LED_GPIO;
    volatile Uint32 LED_GPIO1;
    volatile Uint32 LED_PLLLOCK0;
    volatile Uint32 LED_PLLLOCK1;
    volatile Uint32 LED_CHIP_PASSDONE;
    volatile Uint8 RSVD30[4];
    volatile Uint32 TDIODE;
    volatile Uint32 MARGIN0;
    volatile Uint32 MARGIN1;
    volatile Uint32 MARGIN2;
    volatile Uint32 EFUSE_SECROM_CHKSUM0;
    volatile Uint32 EFUSE_SECROM_CHKSUM1;
    volatile Uint32 EFUSE_SECROM_CHKSUM2;
    volatile Uint32 EFUSE_SECROM_CHKSUM3;
    volatile Uint32 INT_SPARE0;
    volatile Uint32 INT_SPARE1;
    volatile Uint32 LED_MISC_CTL;
    volatile Uint32 CHIP_MISC1;
    volatile Uint32 OBSCLK_CTL;
    volatile Uint32 CHIP_MISC2;
    volatile Uint32 CHIP_MISC3;
    volatile Uint8 RSVD31[4];
    volatile Uint32 EFUSE_RSVD0;
    volatile Uint32 EFUSE_RSVD1;
    volatile Uint32 EFUSE_RSVD2;
    volatile Uint32 EFUSE_RSVD3;
    volatile Uint32 PWRSWTCH_WKUP_MODE0_0;
    volatile Uint32 PWRSWTCH_WKUP_MODE0_1;
    volatile Uint32 PWRSWTCH_WKUP_MODE1_0;
    volatile Uint32 PWRSWTCH_WKUP_MODE1_1;
    volatile Uint8 RSVD32[4943];
    volatile Uint32 END_POINT;
} CSL_BootcfgRegs;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* revision_reg */

#define CSL_BOOTCFG_REVISION_REG_REV_SCHEME_MASK (0xC0000000u)
#define CSL_BOOTCFG_REVISION_REG_REV_SCHEME_SHIFT (0x0000001Eu)
#define CSL_BOOTCFG_REVISION_REG_REV_SCHEME_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_REVISION_REG_REV_MODULE_MASK (0x0FFF0000u)
#define CSL_BOOTCFG_REVISION_REG_REV_MODULE_SHIFT (0x00000010u)
#define CSL_BOOTCFG_REVISION_REG_REV_MODULE_RESETVAL (0x00000E84u)

#define CSL_BOOTCFG_REVISION_REG_REV_RTL_MASK (0x0000F800u)
#define CSL_BOOTCFG_REVISION_REG_REV_RTL_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_REVISION_REG_REV_RTL_RESETVAL (0x00000025u)

#define CSL_BOOTCFG_REVISION_REG_REV_MAJOR_MASK (0x00000700u)
#define CSL_BOOTCFG_REVISION_REG_REV_MAJOR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_REVISION_REG_REV_MAJOR_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_REVISION_REG_REV_CUSTOM_MASK (0x000000C0u)
#define CSL_BOOTCFG_REVISION_REG_REV_CUSTOM_SHIFT (0x00000006u)
#define CSL_BOOTCFG_REVISION_REG_REV_CUSTOM_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_REVISION_REG_REV_MINOR_MASK (0x0000003Fu)
#define CSL_BOOTCFG_REVISION_REG_REV_MINOR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_REVISION_REG_REV_MINOR_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_REVISION_REG_RESETVAL (0x4E852901u)

/* die_id_reg0 */

#define CSL_BOOTCFG_DIE_ID_REG0_DIE_ID0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DIE_ID_REG0_DIE_ID0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DIE_ID_REG0_DIE_ID0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DIE_ID_REG0_RESETVAL (0x00000000u)

/* die_id_reg1 */

#define CSL_BOOTCFG_DIE_ID_REG1_DIE_ID1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DIE_ID_REG1_DIE_ID1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DIE_ID_REG1_DIE_ID1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DIE_ID_REG1_RESETVAL (0x00000000u)

/* die_id_reg2 */

#define CSL_BOOTCFG_DIE_ID_REG2_DIE_ID2_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DIE_ID_REG2_DIE_ID2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DIE_ID_REG2_DIE_ID2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DIE_ID_REG2_RESETVAL (0x00000000u)

/* die_id_reg3 */

#define CSL_BOOTCFG_DIE_ID_REG3_DIE_ID3_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DIE_ID_REG3_DIE_ID3_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DIE_ID_REG3_DIE_ID3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DIE_ID_REG3_RESETVAL (0x00000000u)

/* jtag_id_reg0 */

#define CSL_BOOTCFG_JTAG_ID_REG0_DEVICE_ID0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_JTAG_ID_REG0_DEVICE_ID0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_JTAG_ID_REG0_DEVICE_ID0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_JTAG_ID_REG0_RESETVAL (0x00000000u)

/* jtag_id_reg1 */

#define CSL_BOOTCFG_JTAG_ID_REG1_DEVICE_ID1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_JTAG_ID_REG1_DEVICE_ID1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_JTAG_ID_REG1_DEVICE_ID1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_JTAG_ID_REG1_RESETVAL (0x00000000u)


/* devstat */

#define CSL_BOOTCFG_DEVSTAT_LENDIAN_MASK (0x00000001u)
#define CSL_BOOTCFG_DEVSTAT_LENDIAN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DEVSTAT_LENDIAN_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_DEVSTAT_BOOTMODE_MASK (0x0001FFFEu)
#define CSL_BOOTCFG_DEVSTAT_BOOTMODE_SHIFT (0x00000001u)
#define CSL_BOOTCFG_DEVSTAT_BOOTMODE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVSTAT_AVSIFSEL_MASK (0x00060000u)
#define CSL_BOOTCFG_DEVSTAT_AVSIFSEL_SHIFT (0x00000011u)
#define CSL_BOOTCFG_DEVSTAT_AVSIFSEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVSTAT_MAINPLL_ODSEL_MASK (0x00080000u)
#define CSL_BOOTCFG_DEVSTAT_MAINPLL_ODSEL_SHIFT (0x00000013u)
#define CSL_BOOTCFG_DEVSTAT_MAINPLL_ODSEL_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_DEVSTAT_ARMAVSSHAREDZ_MASK (0x00200000u)
#define CSL_BOOTCFG_DEVSTAT_ARMAVSSHAREDZ_SHIFT (0x00000015u)
#define CSL_BOOTCFG_DEVSTAT_ARMAVSSHAREDZ_RESETVAL (0x00000001u)


#define CSL_BOOTCFG_BOOT_REG0_DDR3A_MAP_EN_MASK (0x02000000u)
#define CSL_BOOTCFG_BOOT_REG0_DDR3A_MAP_EN_SHIFT (0x00000019u)
#define CSL_BOOTCFG_BOOT_REG0_DDR3A_MAP_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVSTAT_RESETVAL (0x00680001u)

/* kick_reg0 */

#define CSL_BOOTCFG_KICK_REG0_KICK0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_KICK_REG0_KICK0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_KICK_REG0_KICK0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_KICK_REG0_RESETVAL (0x00000000u)

/* kick_reg1 */

#define CSL_BOOTCFG_KICK_REG1_KICK1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_KICK_REG1_KICK1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_KICK_REG1_KICK1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_KICK_REG1_RESETVAL (0x00000000u)

/* bootaddr_gem0_reg */

#define CSL_BOOTCFG_BOOTADDR_GEM0_REG_GEM0_BOOT_RDY_MASK (0x00000001u)
#define CSL_BOOTCFG_BOOTADDR_GEM0_REG_GEM0_BOOT_RDY_SHIFT (0x00000000u)
#define CSL_BOOTCFG_BOOTADDR_GEM0_REG_GEM0_BOOT_RDY_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_BOOTADDR_GEM0_REG_BOOTADDR_GEM0_MASK (0xFFFFFC00u)
#define CSL_BOOTCFG_BOOTADDR_GEM0_REG_BOOTADDR_GEM0_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_BOOTADDR_GEM0_REG_BOOTADDR_GEM0_RESETVAL (0x00082C00u)

#define CSL_BOOTCFG_BOOTADDR_GEM0_REG_RESETVAL (0x20B00001u)

/* bootaddr_gem1_reg */

#define CSL_BOOTCFG_BOOTADDR_GEM1_REG_GEM1_BOOT_RDY_MASK (0x00000001u)
#define CSL_BOOTCFG_BOOTADDR_GEM1_REG_GEM1_BOOT_RDY_SHIFT (0x00000000u)
#define CSL_BOOTCFG_BOOTADDR_GEM1_REG_GEM1_BOOT_RDY_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_BOOTADDR_GEM1_REG_BOOTADDR_GEM1_MASK (0xFFFFFC00u)
#define CSL_BOOTCFG_BOOTADDR_GEM1_REG_BOOTADDR_GEM1_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_BOOTADDR_GEM1_REG_BOOTADDR_GEM1_RESETVAL (0x00082C00u)

#define CSL_BOOTCFG_BOOTADDR_GEM1_REG_RESETVAL (0x20B00001u)

/* bootaddr_gem2_reg */

#define CSL_BOOTCFG_BOOTADDR_GEM2_REG_GEM2_BOOT_RDY_MASK (0x00000001u)
#define CSL_BOOTCFG_BOOTADDR_GEM2_REG_GEM2_BOOT_RDY_SHIFT (0x00000000u)
#define CSL_BOOTCFG_BOOTADDR_GEM2_REG_GEM2_BOOT_RDY_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_BOOTADDR_GEM2_REG_BOOTADDR_GEM2_MASK (0xFFFFFC00u)
#define CSL_BOOTCFG_BOOTADDR_GEM2_REG_BOOTADDR_GEM2_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_BOOTADDR_GEM2_REG_BOOTADDR_GEM2_RESETVAL (0x00082C00u)

#define CSL_BOOTCFG_BOOTADDR_GEM2_REG_RESETVAL (0x20B00001u)

/* bootaddr_gem3_reg */

#define CSL_BOOTCFG_BOOTADDR_GEM3_REG_GEM3_BOOT_RDY_MASK (0x00000001u)
#define CSL_BOOTCFG_BOOTADDR_GEM3_REG_GEM3_BOOT_RDY_SHIFT (0x00000000u)
#define CSL_BOOTCFG_BOOTADDR_GEM3_REG_GEM3_BOOT_RDY_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_BOOTADDR_GEM3_REG_BOOTADDR_GEM3_MASK (0xFFFFFC00u)
#define CSL_BOOTCFG_BOOTADDR_GEM3_REG_BOOTADDR_GEM3_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_BOOTADDR_GEM3_REG_BOOTADDR_GEM3_RESETVAL (0x00082C00u)

#define CSL_BOOTCFG_BOOTADDR_GEM3_REG_RESETVAL (0x20B00001u)

/* bootaddr_gem4_reg */

#define CSL_BOOTCFG_BOOTADDR_GEM4_REG_GEM4_BOOT_RDY_MASK (0x00000001u)
#define CSL_BOOTCFG_BOOTADDR_GEM4_REG_GEM4_BOOT_RDY_SHIFT (0x00000000u)
#define CSL_BOOTCFG_BOOTADDR_GEM4_REG_GEM4_BOOT_RDY_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_BOOTADDR_GEM4_REG_BOOTADDR_GEM4_MASK (0xFFFFFC00u)
#define CSL_BOOTCFG_BOOTADDR_GEM4_REG_BOOTADDR_GEM4_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_BOOTADDR_GEM4_REG_BOOTADDR_GEM4_RESETVAL (0x00082C00u)

#define CSL_BOOTCFG_BOOTADDR_GEM4_REG_RESETVAL (0x20B00001u)

/* bootaddr_gem5_reg */

#define CSL_BOOTCFG_BOOTADDR_GEM5_REG_GEM5_BOOT_RDY_MASK (0x00000001u)
#define CSL_BOOTCFG_BOOTADDR_GEM5_REG_GEM5_BOOT_RDY_SHIFT (0x00000000u)
#define CSL_BOOTCFG_BOOTADDR_GEM5_REG_GEM5_BOOT_RDY_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_BOOTADDR_GEM5_REG_BOOTADDR_GEM5_MASK (0xFFFFFC00u)
#define CSL_BOOTCFG_BOOTADDR_GEM5_REG_BOOTADDR_GEM5_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_BOOTADDR_GEM5_REG_BOOTADDR_GEM5_RESETVAL (0x00082C00u)

#define CSL_BOOTCFG_BOOTADDR_GEM5_REG_RESETVAL (0x20B00001u)

/* bootaddr_gem6_reg */

#define CSL_BOOTCFG_BOOTADDR_GEM6_REG_GEM6_BOOT_RDY_MASK (0x00000001u)
#define CSL_BOOTCFG_BOOTADDR_GEM6_REG_GEM6_BOOT_RDY_SHIFT (0x00000000u)
#define CSL_BOOTCFG_BOOTADDR_GEM6_REG_GEM6_BOOT_RDY_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_BOOTADDR_GEM6_REG_BOOTADDR_GEM6_MASK (0xFFFFFC00u)
#define CSL_BOOTCFG_BOOTADDR_GEM6_REG_BOOTADDR_GEM6_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_BOOTADDR_GEM6_REG_BOOTADDR_GEM6_RESETVAL (0x00082C00u)

#define CSL_BOOTCFG_BOOTADDR_GEM6_REG_RESETVAL (0x20B00001u)

/* bootaddr_gem7_reg */

#define CSL_BOOTCFG_BOOTADDR_GEM7_REG_GEM7_BOOT_RDY_MASK (0x00000001u)
#define CSL_BOOTCFG_BOOTADDR_GEM7_REG_GEM7_BOOT_RDY_SHIFT (0x00000000u)
#define CSL_BOOTCFG_BOOTADDR_GEM7_REG_GEM7_BOOT_RDY_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_BOOTADDR_GEM7_REG_BOOTADDR_GEM7_MASK (0xFFFFFC00u)
#define CSL_BOOTCFG_BOOTADDR_GEM7_REG_BOOTADDR_GEM7_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_BOOTADDR_GEM7_REG_BOOTADDR_GEM7_RESETVAL (0x00082C00u)

#define CSL_BOOTCFG_BOOTADDR_GEM7_REG_RESETVAL (0x20B00001u)

/* intr_raw_status_reg */



#define CSL_BOOTCFG_INTR_RAW_STATUS_REG_RESETVAL (0x00000000u)

/* intr_enabled_status_reg */



#define CSL_BOOTCFG_INTR_ENABLED_STATUS_REG_RESETVAL (0x00000000u)

/* intr_enable_reg */



#define CSL_BOOTCFG_INTR_ENABLE_REG_RESETVAL (0x00000000u)

/* intr_enable_clr_reg */



#define CSL_BOOTCFG_INTR_ENABLE_CLR_REG_RESETVAL (0x00000000u)

/* eoi_reg */

#define CSL_BOOTCFG_EOI_REG_EOI_VECTOR_MASK (0x000000FFu)
#define CSL_BOOTCFG_EOI_REG_EOI_VECTOR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EOI_REG_EOI_VECTOR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EOI_REG_RESETVAL (0x00000000u)

/* fault_address_reg */

#define CSL_BOOTCFG_FAULT_ADDRESS_REG_FAULT_ADDR_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_FAULT_ADDRESS_REG_FAULT_ADDR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_FAULT_ADDRESS_REG_FAULT_ADDR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_FAULT_ADDRESS_REG_RESETVAL (0x00000000u)

/* fault_status_reg */

#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_ID_MASK (0x0F000000u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_ID_SHIFT (0x00000018u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_ID_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_MSTID_MASK (0x00FF0000u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_MSTID_SHIFT (0x00000010u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_MSTID_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_PRIVID_MASK (0x00001E00u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_PRIVID_SHIFT (0x00000009u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_PRIVID_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_NS_MASK (0x00000080u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_NS_SHIFT (0x00000007u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_NS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_TYPE_MASK (0x0000003Fu)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_TYPE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_TYPE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_FAULT_STATUS_REG_RESETVAL (0x00000000u)

/* fault_clear_reg */

#define CSL_BOOTCFG_FAULT_CLEAR_REG_FAULT_CLEAR_MASK (0x00000001u)
#define CSL_BOOTCFG_FAULT_CLEAR_REG_FAULT_CLEAR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_FAULT_CLEAR_REG_FAULT_CLEAR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_FAULT_CLEAR_REG_RESETVAL (0x00000000u)

/* mac_id0 */

#define CSL_BOOTCFG_MAC_ID0_MAC_ID0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_MAC_ID0_MAC_ID0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_MAC_ID0_MAC_ID0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MAC_ID0_RESETVAL (0x00000000u)

/* mac_id1 */

#define CSL_BOOTCFG_MAC_ID1_MAC_ID1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_MAC_ID1_MAC_ID1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_MAC_ID1_MAC_ID1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MAC_ID1_RESETVAL (0x00000000u)

/* pcievendorid */

#define CSL_BOOTCFG_PCIEVENDORID_PCIEVENDORID_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_PCIEVENDORID_PCIEVENDORID_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PCIEVENDORID_PCIEVENDORID_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PCIEVENDORID_RESETVAL (0x00000000u)

/* disablestat */

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_AI_20_MASK (0x04000000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_AI_20_SHIFT (0x0000001Au)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_AI_20_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_ARM_SRSS_29_MASK (0x40000000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_ARM_SRSS_29_SHIFT (0x0000001Eu)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_ARM_SRSS_29_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_BCP_25_MASK (0x02000000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_BCP_25_SHIFT (0x00000019u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_BCP_25_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU0_MASK (0x00000100u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU0_SHIFT (0x00000008u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU1_MASK (0x00000200u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU1_SHIFT (0x00000009u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU2_MASK (0x00000400u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU2_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU3_MASK (0x00000800u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU3_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CRYPTO_4_MASK (0x00002000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CRYPTO_4_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CRYPTO_4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_DDR3B_14_MASK (0x00004000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_DDR3B_14_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_DDR3B_14_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_FFTC_AB_17_MASK (0x00400000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_FFTC_AB_17_SHIFT (0x00000016u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_FFTC_AB_17_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_FFTC_CD_18_MASK (0x00800000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_FFTC_CD_18_SHIFT (0x00000017u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_FFTC_CD_18_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_FFTC_EF_19_MASK (0x01000000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_FFTC_EF_19_SHIFT (0x00000018u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_FFTC_EF_19_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM0_5_MASK (0x00000001u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM0_5_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM0_5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM1_6_MASK (0x00000002u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM1_6_SHIFT (0x00000001u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM1_6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM2_7_MASK (0x00000004u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM2_7_SHIFT (0x00000002u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM2_7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM3_8_MASK (0x00000008u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM3_8_SHIFT (0x00000003u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM3_8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM4_9_MASK (0x00000010u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM4_9_SHIFT (0x00000004u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM4_9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM5_10_MASK (0x00000020u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM5_10_SHIFT (0x00000005u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM5_10_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM6_11_MASK (0x00000040u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM6_11_SHIFT (0x00000006u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM6_11_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM7_12_MASK (0x00000080u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM7_12_SHIFT (0x00000007u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM7_12_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_RAC_CD_16_MASK (0x00080000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_RAC_CD_16_SHIFT (0x00000013u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_RAC_CD_16_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_TAC_RAC_AB_15_MASK (0x00040000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_TAC_RAC_AB_15_SHIFT (0x00000012u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_TAC_RAC_AB_15_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_TCP3D_AB_21_MASK (0x00100000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_TCP3D_AB_21_SHIFT (0x00000014u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_TCP3D_AB_21_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_TCP3D_CD_22_MASK (0x00200000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_TCP3D_CD_22_SHIFT (0x00000015u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_TCP3D_CD_22_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_TETRIS_30_MASK (0x00001000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_TETRIS_30_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_TETRIS_30_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_TSIP_3_MASK (0x20000000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_TSIP_3_SHIFT (0x0000001Du)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_TSIP_3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_USB_2_MASK (0x08000000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_USB_2_SHIFT (0x0000001Bu)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_USB_2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_VCP2_ABCD_23_MASK (0x00010000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_VCP2_ABCD_23_SHIFT (0x00000010u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_VCP2_ABCD_23_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_VCP2_EFGH_24_MASK (0x00020000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_VCP2_EFGH_24_SHIFT (0x00000011u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_VCP2_EFGH_24_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_VUSR2_27_MASK (0x10000000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_VUSR2_27_SHIFT (0x0000001Cu)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_VUSR2_27_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_XGE_28_MASK (0x00008000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_XGE_28_SHIFT (0x0000000Fu)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_XGE_28_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_RESETVAL (0x00000000u)

/* lrstnmistat_clr */

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_0_CLR_MASK (0x00000001u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_0_CLR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_0_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_1_CLR_MASK (0x00000002u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_1_CLR_SHIFT (0x00000001u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_1_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_2_CLR_MASK (0x00000004u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_2_CLR_SHIFT (0x00000002u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_2_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_3_CLR_MASK (0x00000008u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_3_CLR_SHIFT (0x00000003u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_3_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_4_CLR_MASK (0x00000010u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_4_CLR_SHIFT (0x00000004u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_4_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_5_CLR_MASK (0x00000020u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_5_CLR_SHIFT (0x00000005u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_5_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_6_CLR_MASK (0x00000040u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_6_CLR_SHIFT (0x00000006u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_6_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_7_CLR_MASK (0x00000080u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_7_CLR_SHIFT (0x00000007u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_7_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_0_CLR_MASK (0x00000100u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_0_CLR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_0_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_1_CLR_MASK (0x00000200u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_1_CLR_SHIFT (0x00000009u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_1_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_2_CLR_MASK (0x00000400u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_2_CLR_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_2_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_3_CLR_MASK (0x00000800u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_3_CLR_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_3_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_4_CLR_MASK (0x00001000u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_4_CLR_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_4_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_5_CLR_MASK (0x00002000u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_5_CLR_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_5_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_6_CLR_MASK (0x00004000u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_6_CLR_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_6_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_7_CLR_MASK (0x00008000u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_7_CLR_SHIFT (0x0000000Fu)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_7_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_RESETVAL (0x00000000u)

/* reset_stat_clr */

#define CSL_BOOTCFG_RESET_STAT_CLR_GRST_STAT_CLR_MASK (0x80000000u)
#define CSL_BOOTCFG_RESET_STAT_CLR_GRST_STAT_CLR_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_RESET_STAT_CLR_GRST_STAT_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_0_CLR_MASK (0x00000001u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_0_CLR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_0_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_1_CLR_MASK (0x00000002u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_1_CLR_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_1_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_2_CLR_MASK (0x00000004u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_2_CLR_SHIFT (0x00000002u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_2_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_3_CLR_MASK (0x00000008u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_3_CLR_SHIFT (0x00000003u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_3_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_4_CLR_MASK (0x00000010u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_4_CLR_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_4_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_5_CLR_MASK (0x00000020u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_5_CLR_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_5_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_6_CLR_MASK (0x00000040u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_6_CLR_SHIFT (0x00000006u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_6_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_7_CLR_MASK (0x00000080u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_7_CLR_SHIFT (0x00000007u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_7_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_CLR_RESETVAL (0x00000000u)

/* boot_complete */

#define CSL_BOOTCFG_BOOT_COMPLETE_GEM0_COMPLETE_MASK (0x00000001u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM0_COMPLETE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM0_COMPLETE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOT_COMPLETE_GEM1_COMPLETE_MASK (0x00000002u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM1_COMPLETE_SHIFT (0x00000001u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM1_COMPLETE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOT_COMPLETE_GEM2_COMPLETE_MASK (0x00000004u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM2_COMPLETE_SHIFT (0x00000002u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM2_COMPLETE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOT_COMPLETE_GEM3_COMPLETE_MASK (0x00000008u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM3_COMPLETE_SHIFT (0x00000003u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM3_COMPLETE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOT_COMPLETE_GEM4_COMPLETE_MASK (0x00000010u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM4_COMPLETE_SHIFT (0x00000004u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM4_COMPLETE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOT_COMPLETE_GEM5_COMPLETE_MASK (0x00000020u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM5_COMPLETE_SHIFT (0x00000005u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM5_COMPLETE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOT_COMPLETE_GEM6_COMPLETE_MASK (0x00000040u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM6_COMPLETE_SHIFT (0x00000006u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM6_COMPLETE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOT_COMPLETE_GEM7_COMPLETE_MASK (0x00000080u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM7_COMPLETE_SHIFT (0x00000007u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM7_COMPLETE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOT_COMPLETE_ARM0_COMPLETE_MASK (0x00000100u)
#define CSL_BOOTCFG_BOOT_COMPLETE_ARM0_COMPLETE_SHIFT (0x00000008u)
#define CSL_BOOTCFG_BOOT_COMPLETE_ARM0_COMPLETE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOT_COMPLETE_ARM1_COMPLETE_MASK (0x00000200u)
#define CSL_BOOTCFG_BOOT_COMPLETE_ARM1_COMPLETE_SHIFT (0x00000009u)
#define CSL_BOOTCFG_BOOT_COMPLETE_ARM1_COMPLETE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOT_COMPLETE_ARM2_COMPLETE_MASK (0x00000400u)
#define CSL_BOOTCFG_BOOT_COMPLETE_ARM2_COMPLETE_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_BOOT_COMPLETE_ARM2_COMPLETE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOT_COMPLETE_ARM3_COMPLETE_MASK (0x00000800u)
#define CSL_BOOTCFG_BOOT_COMPLETE_ARM3_COMPLETE_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_BOOT_COMPLETE_ARM3_COMPLETE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOT_COMPLETE_RESETVAL (0x00000000u)

/* boot_progress */

#define CSL_BOOTCFG_BOOT_PROGRESS_BOOT_PROGRESS_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_BOOT_PROGRESS_BOOT_PROGRESS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_BOOT_PROGRESS_BOOT_PROGRESS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOT_PROGRESS_RESETVAL (0x00000000u)

/* reset_stat */

#define CSL_BOOTCFG_RESET_STAT_GRST_STAT_MASK (0x80000000u)
#define CSL_BOOTCFG_RESET_STAT_GRST_STAT_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_RESET_STAT_GRST_STAT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_LRST_STAT0_MASK (0x00000001u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_LRST_STAT1_MASK (0x00000002u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT1_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_LRST_STAT2_MASK (0x00000004u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT2_SHIFT (0x00000002u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_LRST_STAT3_MASK (0x00000008u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT3_SHIFT (0x00000003u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_LRST_STAT4_MASK (0x00000010u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT4_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_LRST_STAT5_MASK (0x00000020u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT5_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_LRST_STAT6_MASK (0x00000040u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT6_SHIFT (0x00000006u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_LRST_STAT7_MASK (0x00000080u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT7_SHIFT (0x00000007u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_RESETVAL (0x00000000u)

/* lrstnmistat */

#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT0_MASK (0x00000001u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT1_MASK (0x00000002u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT1_SHIFT (0x00000001u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT2_MASK (0x00000004u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT2_SHIFT (0x00000002u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT3_MASK (0x00000008u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT3_SHIFT (0x00000003u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT4_MASK (0x00000010u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT4_SHIFT (0x00000004u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT5_MASK (0x00000020u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT5_SHIFT (0x00000005u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT6_MASK (0x00000040u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT6_SHIFT (0x00000006u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT7_MASK (0x00000080u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT7_SHIFT (0x00000007u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT0_MASK (0x00000100u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT0_SHIFT (0x00000008u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT1_MASK (0x00000200u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT1_SHIFT (0x00000009u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT2_MASK (0x00000400u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT2_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT3_MASK (0x00000800u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT3_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT4_MASK (0x00001000u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT4_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT5_MASK (0x00002000u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT5_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT6_MASK (0x00004000u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT6_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT7_MASK (0x00008000u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT7_SHIFT (0x0000000Fu)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_RESETVAL (0x00000000u)

/* devcfg */

#define CSL_BOOTCFG_DEVCFG_PCIESSMODE_MASK (0x00000006u)
#define CSL_BOOTCFG_DEVCFG_PCIESSMODE_SHIFT (0x00000001u)
#define CSL_BOOTCFG_DEVCFG_PCIESSMODE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVCFG_SYSCLKOUTEN_MASK (0x00000001u)
#define CSL_BOOTCFG_DEVCFG_SYSCLKOUTEN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DEVCFG_SYSCLKOUTEN_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_DEVCFG_RESETVAL  (0x00000001u)

/* pwr_stat */

#define CSL_BOOTCFG_PWR_STAT_HIBERNATION_MASK (0x00000002u)
#define CSL_BOOTCFG_PWR_STAT_HIBERNATION_SHIFT (0x00000001u)
#define CSL_BOOTCFG_PWR_STAT_HIBERNATION_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWR_STAT_HIBERNATION_MODE_MASK (0x00000004u)
#define CSL_BOOTCFG_PWR_STAT_HIBERNATION_MODE_SHIFT (0x00000002u)
#define CSL_BOOTCFG_PWR_STAT_HIBERNATION_MODE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWR_STAT_PWR_STAT_GENERAL_MASK (0xFFFFFFF8u)
#define CSL_BOOTCFG_PWR_STAT_PWR_STAT_GENERAL_SHIFT (0x00000003u)
#define CSL_BOOTCFG_PWR_STAT_PWR_STAT_GENERAL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWR_STAT_STANDBY_MASK (0x00000001u)
#define CSL_BOOTCFG_PWR_STAT_STANDBY_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PWR_STAT_STANDBY_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWR_STAT_RESETVAL (0x00000000u)

/* class0_efuse_reg */

#define CSL_BOOTCFG_CLASS0_EFUSE0_REG_CLASS0_EFUSE0_REG_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_CLASS0_EFUSE0_REG_CLASS0_EFUSE0_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_CLASS0_EFUSE0_REG_CLASS0_EFUSE0_REG_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CLASS0_EFUSE0_REG_RESETVAL (0x00000000u)

/* sen0_0_efuse_reg0 */

#define CSL_BOOTCFG_SEN0_0_EFUSE_REG0_SEN0_0_EFUSE_REG0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN0_0_EFUSE_REG0_SEN0_0_EFUSE_REG0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN0_0_EFUSE_REG0_SEN0_0_EFUSE_REG0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN0_0_EFUSE_REG0_RESETVAL (0x00000000u)

/* sen1_0_efuse_reg1 */

#define CSL_BOOTCFG_SEN1_0_EFUSE_REG1_SEN1_0_EFUSE_REG1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN1_0_EFUSE_REG1_SEN1_0_EFUSE_REG1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN1_0_EFUSE_REG1_SEN1_0_EFUSE_REG1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN1_0_EFUSE_REG1_RESETVAL (0x00000000u)

/* sen2_0_efuse_reg2 */

#define CSL_BOOTCFG_SEN2_0_EFUSE_REG2_SEN2_0_EFUSE_REG2_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN2_0_EFUSE_REG2_SEN2_0_EFUSE_REG2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN2_0_EFUSE_REG2_SEN2_0_EFUSE_REG2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN2_0_EFUSE_REG2_RESETVAL (0x00000000u)

/* sen3_0_efuse_reg3 */

#define CSL_BOOTCFG_SEN3_0_EFUSE_REG3_SEN3_0_EFUSE_REG3_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN3_0_EFUSE_REG3_SEN3_0_EFUSE_REG3_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN3_0_EFUSE_REG3_SEN3_0_EFUSE_REG3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN3_0_EFUSE_REG3_RESETVAL (0x00000000u)

/* sen0_1_efuse_reg4 */

#define CSL_BOOTCFG_SEN0_1_EFUSE_REG4_SEN0_1_EFUSE_REG4_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN0_1_EFUSE_REG4_SEN0_1_EFUSE_REG4_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN0_1_EFUSE_REG4_SEN0_1_EFUSE_REG4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN0_1_EFUSE_REG4_RESETVAL (0x00000000u)

/* sen1_1_efuse_reg5 */

#define CSL_BOOTCFG_SEN1_1_EFUSE_REG5_SEN1_1_EFUSE_REG5_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN1_1_EFUSE_REG5_SEN1_1_EFUSE_REG5_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN1_1_EFUSE_REG5_SEN1_1_EFUSE_REG5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN1_1_EFUSE_REG5_RESETVAL (0x00000000u)

/* sen2_1_efuse_reg6 */

#define CSL_BOOTCFG_SEN2_1_EFUSE_REG6_SEN2_1_EFUSE_REG6_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN2_1_EFUSE_REG6_SEN2_1_EFUSE_REG6_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN2_1_EFUSE_REG6_SEN2_1_EFUSE_REG6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN2_1_EFUSE_REG6_RESETVAL (0x00000000u)

/* sen3_1_efuse_reg7 */

#define CSL_BOOTCFG_SEN3_1_EFUSE_REG7_SEN3_1_EFUSE_REG7_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN3_1_EFUSE_REG7_SEN3_1_EFUSE_REG7_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN3_1_EFUSE_REG7_SEN3_1_EFUSE_REG7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN3_1_EFUSE_REG7_RESETVAL (0x00000000u)

/* sen0_2_efuse_reg8 */

#define CSL_BOOTCFG_SEN0_2_EFUSE_REG8_SEN0_2_EFUSE_REG8_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN0_2_EFUSE_REG8_SEN0_2_EFUSE_REG8_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN0_2_EFUSE_REG8_SEN0_2_EFUSE_REG8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN0_2_EFUSE_REG8_RESETVAL (0x00000000u)

/* sen1_2_efuse_reg9 */

#define CSL_BOOTCFG_SEN1_2_EFUSE_REG9_SEN1_2_EFUSE_REG9_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN1_2_EFUSE_REG9_SEN1_2_EFUSE_REG9_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN1_2_EFUSE_REG9_SEN1_2_EFUSE_REG9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN1_2_EFUSE_REG9_RESETVAL (0x00000000u)

/* sen2_2_efuse_reg10 */

#define CSL_BOOTCFG_SEN2_2_EFUSE_REG10_SEN2_2_EFUSE_REG10_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN2_2_EFUSE_REG10_SEN2_2_EFUSE_REG10_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN2_2_EFUSE_REG10_SEN2_2_EFUSE_REG10_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN2_2_EFUSE_REG10_RESETVAL (0x00000000u)

/* sen3_2_efuse_reg11 */

#define CSL_BOOTCFG_SEN3_2_EFUSE_REG11_SEN3_2_EFUSE_REG11_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN3_2_EFUSE_REG11_SEN3_2_EFUSE_REG11_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN3_2_EFUSE_REG11_SEN3_2_EFUSE_REG11_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN3_2_EFUSE_REG11_RESETVAL (0x00000000u)

/* sen0_3_efuse_reg12 */

#define CSL_BOOTCFG_SEN0_3_EFUSE_REG12_SEN0_3_EFUSE_REG12_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN0_3_EFUSE_REG12_SEN0_3_EFUSE_REG12_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN0_3_EFUSE_REG12_SEN0_3_EFUSE_REG12_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN0_3_EFUSE_REG12_RESETVAL (0x00000000u)

/* sen1_3_efuse_reg13 */

#define CSL_BOOTCFG_SEN1_3_EFUSE_REG13_SEN1_3_EFUSE_REG13_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN1_3_EFUSE_REG13_SEN1_3_EFUSE_REG13_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN1_3_EFUSE_REG13_SEN1_3_EFUSE_REG13_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN1_3_EFUSE_REG13_RESETVAL (0x00000000u)

/* sen2_3_efuse_reg14 */

#define CSL_BOOTCFG_SEN2_3_EFUSE_REG14_SEN2_3_EFUSE_REG14_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN2_3_EFUSE_REG14_SEN2_3_EFUSE_REG14_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN2_3_EFUSE_REG14_SEN2_3_EFUSE_REG14_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN2_3_EFUSE_REG14_RESETVAL (0x00000000u)

/* sen3_3_efuse_reg15 */

#define CSL_BOOTCFG_SEN3_3_EFUSE_REG15_SEN3_3_EFUSE_REG15_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN3_3_EFUSE_REG15_SEN3_3_EFUSE_REG15_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN3_3_EFUSE_REG15_SEN3_3_EFUSE_REG15_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN3_3_EFUSE_REG15_RESETVAL (0x00000000u)

/* nmigr_0 */

#define CSL_BOOTCFG_NMIGR_0_NMIGR_0_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_NMIGR_0_NMIGR_0_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_NMIGR_0_NMIGR_0_REG_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_NMIGR_0_RESETVAL (0x00000000u)

/* nmigr_1 */

#define CSL_BOOTCFG_NMIGR_1_NMIGR_1_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_NMIGR_1_NMIGR_1_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_NMIGR_1_NMIGR_1_REG_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_NMIGR_1_RESETVAL (0x00000000u)

/* nmigr_2 */

#define CSL_BOOTCFG_NMIGR_2_NMIGR_2_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_NMIGR_2_NMIGR_2_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_NMIGR_2_NMIGR_2_REG_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_NMIGR_2_RESETVAL (0x00000000u)

/* nmigr_3 */

#define CSL_BOOTCFG_NMIGR_3_NMIGR_3_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_NMIGR_3_NMIGR_3_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_NMIGR_3_NMIGR_3_REG_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_NMIGR_3_RESETVAL (0x00000000u)

/* nmigr_4 */

#define CSL_BOOTCFG_NMIGR_4_NMIGR_4_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_NMIGR_4_NMIGR_4_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_NMIGR_4_NMIGR_4_REG_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_NMIGR_4_RESETVAL (0x00000000u)

/* nmigr_5 */

#define CSL_BOOTCFG_NMIGR_5_NMIGR_5_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_NMIGR_5_NMIGR_5_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_NMIGR_5_NMIGR_5_REG_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_NMIGR_5_RESETVAL (0x00000000u)

/* nmigr_6 */

#define CSL_BOOTCFG_NMIGR_6_NMIGR_6_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_NMIGR_6_NMIGR_6_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_NMIGR_6_NMIGR_6_REG_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_NMIGR_6_RESETVAL (0x00000000u)

/* nmigr_7 */

#define CSL_BOOTCFG_NMIGR_7_NMIGR_7_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_NMIGR_7_NMIGR_7_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_NMIGR_7_NMIGR_7_REG_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_NMIGR_7_RESETVAL (0x00000000u)

/* ipcgr0 */

#define CSL_BOOTCFG_IPCGR0_IPCGR0_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGR0_IPCGR0_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGR0_IPCGR0_REG_RESETVAL (0x00000000u)

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_IPCGR0_IPCGR0_SRC_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_IPCGR0_IPCGR0_SRC_SHIFT (0x00000004u)
#define CSL_BOOTCFG_IPCGR0_IPCGR0_SRC_RESETVAL (0x00000000u)
#endif

#define CSL_BOOTCFG_IPCGR0_RESETVAL  (0x00000000u)

/* ipcgr1 */

#define CSL_BOOTCFG_IPCGR1_IPCGR1_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGR1_IPCGR1_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGR1_IPCGR1_REG_RESETVAL (0x00000000u)


#define CSL_BOOTCFG_IPCGR1_RESETVAL  (0x00000000u)

/* ipcgr2 */

#define CSL_BOOTCFG_IPCGR2_IPCGR2_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGR2_IPCGR2_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGR2_IPCGR2_REG_RESETVAL (0x00000000u)


#define CSL_BOOTCFG_IPCGR2_RESETVAL  (0x00000000u)

/* ipcgr3 */

#define CSL_BOOTCFG_IPCGR3_IPCGR3_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGR3_IPCGR3_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGR3_IPCGR3_REG_RESETVAL (0x00000000u)


#define CSL_BOOTCFG_IPCGR3_RESETVAL  (0x00000000u)

/* ipcgr4 */

#define CSL_BOOTCFG_IPCGR4_IPCGR4_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGR4_IPCGR4_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGR4_IPCGR4_REG_RESETVAL (0x00000000u)


#define CSL_BOOTCFG_IPCGR4_RESETVAL  (0x00000000u)

/* ipcgr5 */

#define CSL_BOOTCFG_IPCGR5_IPCGR5_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGR5_IPCGR5_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGR5_IPCGR5_REG_RESETVAL (0x00000000u)


#define CSL_BOOTCFG_IPCGR5_RESETVAL  (0x00000000u)

/* ipcgr6 */

#define CSL_BOOTCFG_IPCGR6_IPCGR6_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGR6_IPCGR6_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGR6_IPCGR6_REG_RESETVAL (0x00000000u)


#define CSL_BOOTCFG_IPCGR6_RESETVAL  (0x00000000u)

/* ipcgr7 */

#define CSL_BOOTCFG_IPCGR7_IPCGR7_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGR7_IPCGR7_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGR7_IPCGR7_REG_RESETVAL (0x00000000u)


#define CSL_BOOTCFG_IPCGR7_RESETVAL  (0x00000000u)

/* ipcgr8 */

#define CSL_BOOTCFG_IPCGR8_IPCGR8_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGR8_IPCGR8_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGR8_IPCGR8_REG_RESETVAL (0x00000000u)


#define CSL_BOOTCFG_IPCGR8_RESETVAL  (0x00000000u)

/* ipcgr9 */

#define CSL_BOOTCFG_IPCGR9_IPCGR9_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGR9_IPCGR9_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGR9_IPCGR9_REG_RESETVAL (0x00000000u)


#define CSL_BOOTCFG_IPCGR9_RESETVAL  (0x00000000u)

/* ipcgr10 */

#define CSL_BOOTCFG_IPCGR10_IPCGR10_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGR10_IPCGR10_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGR10_IPCGR10_REG_RESETVAL (0x00000000u)


#define CSL_BOOTCFG_IPCGR10_RESETVAL (0x00000000u)

/* ipcgr11 */

#define CSL_BOOTCFG_IPCGR11_IPCGR11_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGR11_IPCGR11_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGR11_IPCGR11_REG_RESETVAL (0x00000000u)


#define CSL_BOOTCFG_IPCGR11_RESETVAL (0x00000000u)

/* ipcgrh */

#define CSL_BOOTCFG_IPCGRH_IPCGRH_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGRH_IPCGRH_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGRH_IPCGRH_REG_RESETVAL (0x00000000u)


#define CSL_BOOTCFG_IPCGRH_RESETVAL  (0x00000000u)

/* ipcar0 */


#define CSL_BOOTCFG_IPCAR0_RESETVAL  (0x00000000u)

/* ipcar1 */


#define CSL_BOOTCFG_IPCAR1_RESETVAL  (0x00000000u)

/* ipcar2 */


#define CSL_BOOTCFG_IPCAR2_RESETVAL  (0x00000000u)

/* ipcar3 */


#define CSL_BOOTCFG_IPCAR3_RESETVAL  (0x00000000u)

/* ipcar4 */


#define CSL_BOOTCFG_IPCAR4_RESETVAL  (0x00000000u)

/* ipcar5 */


#define CSL_BOOTCFG_IPCAR5_RESETVAL  (0x00000000u)

/* ipcar6 */


#define CSL_BOOTCFG_IPCAR6_RESETVAL  (0x00000000u)

/* ipcar7 */


#define CSL_BOOTCFG_IPCAR7_RESETVAL  (0x00000000u)

/* ipcar8 */


#define CSL_BOOTCFG_IPCAR8_RESETVAL  (0x00000000u)

/* ipcar9 */


#define CSL_BOOTCFG_IPCAR9_RESETVAL  (0x00000000u)

/* ipcar10 */


#define CSL_BOOTCFG_IPCAR10_RESETVAL (0x00000000u)

/* ipcar11 */


#define CSL_BOOTCFG_IPCAR11_RESETVAL (0x00000000u)

/* ipcarh */


#define CSL_BOOTCFG_IPCARH_RESETVAL  (0x00000000u)

/* tinpsel_msb */

#define CSL_BOOTCFG_TINPSEL_MSB_TINPSEL_MSB_MASK (0x000000FFu)
#define CSL_BOOTCFG_TINPSEL_MSB_TINPSEL_MSB_SHIFT (0x00000000u)
#define CSL_BOOTCFG_TINPSEL_MSB_TINPSEL_MSB_RESETVAL (0x000000AAu)

#define CSL_BOOTCFG_TINPSEL_MSB_RESETVAL (0x000000AAu)

/* tinpsel */

#define CSL_BOOTCFG_TINPSEL_TINPSEL_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_TINPSEL_TINPSEL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_TINPSEL_TINPSEL_RESETVAL (0xAAAAAAAAu)

#define CSL_BOOTCFG_TINPSEL_RESETVAL (0xAAAAAAAAu)

/* toutsel */

#define CSL_BOOTCFG_TOUTSEL_TOUTSEL0_MASK (0x0000001Fu)
#define CSL_BOOTCFG_TOUTSEL_TOUTSEL0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_TOUTSEL_TOUTSEL0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TOUTSEL_TOUTSEL1_MASK (0x000003E0u)
#define CSL_BOOTCFG_TOUTSEL_TOUTSEL1_SHIFT (0x00000005u)
#define CSL_BOOTCFG_TOUTSEL_TOUTSEL1_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_TOUTSEL_RESETVAL (0x00000020u)

/* rstmux0 */

#define CSL_BOOTCFG_RSTMUX0_RSTMUX_DELAY0_MASK (0x000000E0u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_DELAY0_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_DELAY0_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_RSTMUX0_RSTMUX_EVSTAT0_MASK (0x00000010u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_EVSTAT0_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_EVSTAT0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX0_RSTMUX_EVSTAT_CLR0_MASK (0x00000200u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_EVSTAT_CLR0_SHIFT (0x00000009u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_EVSTAT_CLR0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX0_RSTMUX_LOCK0_MASK (0x00000001u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_LOCK0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_LOCK0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX0_RSTMUX_OMODE0_MASK (0x0000000Eu)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_OMODE0_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_OMODE0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX0_RESETVAL (0x00000080u)

/* rstmux1 */

#define CSL_BOOTCFG_RSTMUX1_RSTMUX_DELAY1_MASK (0x000000E0u)
#define CSL_BOOTCFG_RSTMUX1_RSTMUX_DELAY1_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RSTMUX1_RSTMUX_DELAY1_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_RSTMUX1_RSTMUX_EVSTAT1_MASK (0x00000010u)
#define CSL_BOOTCFG_RSTMUX1_RSTMUX_EVSTAT1_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RSTMUX1_RSTMUX_EVSTAT1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX1_RSTMUX_EVSTAT_CLR1_MASK (0x00000200u)
#define CSL_BOOTCFG_RSTMUX1_RSTMUX_EVSTAT_CLR1_SHIFT (0x00000009u)
#define CSL_BOOTCFG_RSTMUX1_RSTMUX_EVSTAT_CLR1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX1_RSTMUX_LOCK1_MASK (0x00000001u)
#define CSL_BOOTCFG_RSTMUX1_RSTMUX_LOCK1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RSTMUX1_RSTMUX_LOCK1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX1_RSTMUX_OMODE1_MASK (0x0000000Eu)
#define CSL_BOOTCFG_RSTMUX1_RSTMUX_OMODE1_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RSTMUX1_RSTMUX_OMODE1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX1_RESETVAL (0x00000080u)

/* rstmux2 */

#define CSL_BOOTCFG_RSTMUX2_RSTMUX_DELAY2_MASK (0x000000E0u)
#define CSL_BOOTCFG_RSTMUX2_RSTMUX_DELAY2_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RSTMUX2_RSTMUX_DELAY2_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_RSTMUX2_RSTMUX_EVSTAT2_MASK (0x00000010u)
#define CSL_BOOTCFG_RSTMUX2_RSTMUX_EVSTAT2_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RSTMUX2_RSTMUX_EVSTAT2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX2_RSTMUX_EVSTAT_CLR2_MASK (0x00000200u)
#define CSL_BOOTCFG_RSTMUX2_RSTMUX_EVSTAT_CLR2_SHIFT (0x00000009u)
#define CSL_BOOTCFG_RSTMUX2_RSTMUX_EVSTAT_CLR2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX2_RSTMUX_LOCK2_MASK (0x00000001u)
#define CSL_BOOTCFG_RSTMUX2_RSTMUX_LOCK2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RSTMUX2_RSTMUX_LOCK2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX2_RSTMUX_OMODE2_MASK (0x0000000Eu)
#define CSL_BOOTCFG_RSTMUX2_RSTMUX_OMODE2_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RSTMUX2_RSTMUX_OMODE2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX2_RESETVAL (0x00000080u)

/* rstmux3 */

#define CSL_BOOTCFG_RSTMUX3_RSTMUX_DELAY3_MASK (0x000000E0u)
#define CSL_BOOTCFG_RSTMUX3_RSTMUX_DELAY3_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RSTMUX3_RSTMUX_DELAY3_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_RSTMUX3_RSTMUX_EVSTAT3_MASK (0x00000010u)
#define CSL_BOOTCFG_RSTMUX3_RSTMUX_EVSTAT3_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RSTMUX3_RSTMUX_EVSTAT3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX3_RSTMUX_EVSTAT_CLR3_MASK (0x00000200u)
#define CSL_BOOTCFG_RSTMUX3_RSTMUX_EVSTAT_CLR3_SHIFT (0x00000009u)
#define CSL_BOOTCFG_RSTMUX3_RSTMUX_EVSTAT_CLR3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX3_RSTMUX_LOCK3_MASK (0x00000001u)
#define CSL_BOOTCFG_RSTMUX3_RSTMUX_LOCK3_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RSTMUX3_RSTMUX_LOCK3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX3_RSTMUX_OMODE3_MASK (0x0000000Eu)
#define CSL_BOOTCFG_RSTMUX3_RSTMUX_OMODE3_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RSTMUX3_RSTMUX_OMODE3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX3_RESETVAL (0x00000080u)

/* rstmux4 */

#define CSL_BOOTCFG_RSTMUX4_RSTMUX_DELAY4_MASK (0x000000E0u)
#define CSL_BOOTCFG_RSTMUX4_RSTMUX_DELAY4_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RSTMUX4_RSTMUX_DELAY4_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_RSTMUX4_RSTMUX_EVSTAT4_MASK (0x00000010u)
#define CSL_BOOTCFG_RSTMUX4_RSTMUX_EVSTAT4_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RSTMUX4_RSTMUX_EVSTAT4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX4_RSTMUX_EVSTAT_CLR4_MASK (0x00000200u)
#define CSL_BOOTCFG_RSTMUX4_RSTMUX_EVSTAT_CLR4_SHIFT (0x00000009u)
#define CSL_BOOTCFG_RSTMUX4_RSTMUX_EVSTAT_CLR4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX4_RSTMUX_LOCK4_MASK (0x00000001u)
#define CSL_BOOTCFG_RSTMUX4_RSTMUX_LOCK4_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RSTMUX4_RSTMUX_LOCK4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX4_RSTMUX_OMODE4_MASK (0x0000000Eu)
#define CSL_BOOTCFG_RSTMUX4_RSTMUX_OMODE4_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RSTMUX4_RSTMUX_OMODE4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX4_RESETVAL (0x00000080u)

/* rstmux5 */

#define CSL_BOOTCFG_RSTMUX5_RSTMUX_DELAY5_MASK (0x000000E0u)
#define CSL_BOOTCFG_RSTMUX5_RSTMUX_DELAY5_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RSTMUX5_RSTMUX_DELAY5_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_RSTMUX5_RSTMUX_EVSTAT5_MASK (0x00000010u)
#define CSL_BOOTCFG_RSTMUX5_RSTMUX_EVSTAT5_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RSTMUX5_RSTMUX_EVSTAT5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX5_RSTMUX_EVSTAT_CLR5_MASK (0x00000200u)
#define CSL_BOOTCFG_RSTMUX5_RSTMUX_EVSTAT_CLR5_SHIFT (0x00000009u)
#define CSL_BOOTCFG_RSTMUX5_RSTMUX_EVSTAT_CLR5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX5_RSTMUX_LOCK5_MASK (0x00000001u)
#define CSL_BOOTCFG_RSTMUX5_RSTMUX_LOCK5_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RSTMUX5_RSTMUX_LOCK5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX5_RSTMUX_OMODE5_MASK (0x0000000Eu)
#define CSL_BOOTCFG_RSTMUX5_RSTMUX_OMODE5_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RSTMUX5_RSTMUX_OMODE5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX5_RESETVAL (0x00000080u)

/* rstmux6 */

#define CSL_BOOTCFG_RSTMUX6_RSTMUX_DELAY6_MASK (0x000000E0u)
#define CSL_BOOTCFG_RSTMUX6_RSTMUX_DELAY6_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RSTMUX6_RSTMUX_DELAY6_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_RSTMUX6_RSTMUX_EVSTAT6_MASK (0x00000010u)
#define CSL_BOOTCFG_RSTMUX6_RSTMUX_EVSTAT6_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RSTMUX6_RSTMUX_EVSTAT6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX6_RSTMUX_EVSTAT_CLR6_MASK (0x00000200u)
#define CSL_BOOTCFG_RSTMUX6_RSTMUX_EVSTAT_CLR6_SHIFT (0x00000009u)
#define CSL_BOOTCFG_RSTMUX6_RSTMUX_EVSTAT_CLR6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX6_RSTMUX_LOCK6_MASK (0x00000001u)
#define CSL_BOOTCFG_RSTMUX6_RSTMUX_LOCK6_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RSTMUX6_RSTMUX_LOCK6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX6_RSTMUX_OMODE6_MASK (0x0000000Eu)
#define CSL_BOOTCFG_RSTMUX6_RSTMUX_OMODE6_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RSTMUX6_RSTMUX_OMODE6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX6_RESETVAL (0x00000080u)

/* rstmux7 */

#define CSL_BOOTCFG_RSTMUX7_RSTMUX_DELAY7_MASK (0x000000E0u)
#define CSL_BOOTCFG_RSTMUX7_RSTMUX_DELAY7_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RSTMUX7_RSTMUX_DELAY7_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_RSTMUX7_RSTMUX_EVSTAT7_MASK (0x00000010u)
#define CSL_BOOTCFG_RSTMUX7_RSTMUX_EVSTAT7_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RSTMUX7_RSTMUX_EVSTAT7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX7_RSTMUX_EVSTAT_CLR7_MASK (0x00000200u)
#define CSL_BOOTCFG_RSTMUX7_RSTMUX_EVSTAT_CLR7_SHIFT (0x00000009u)
#define CSL_BOOTCFG_RSTMUX7_RSTMUX_EVSTAT_CLR7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX7_RSTMUX_LOCK7_MASK (0x00000001u)
#define CSL_BOOTCFG_RSTMUX7_RSTMUX_LOCK7_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RSTMUX7_RSTMUX_LOCK7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX7_RSTMUX_OMODE7_MASK (0x0000000Eu)
#define CSL_BOOTCFG_RSTMUX7_RSTMUX_OMODE7_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RSTMUX7_RSTMUX_OMODE7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX7_RESETVAL (0x00000080u)

/* rstmux8 */

#define CSL_BOOTCFG_RSTMUX8_RSTMUX_DELAY8_MASK (0x000000E0u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_DELAY8_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_DELAY8_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_RSTMUX8_RSTMUX_EVSTAT8_MASK (0x00000010u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_EVSTAT8_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_EVSTAT8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX8_RSTMUX_EVSTAT_CLR8_MASK (0x00000200u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_EVSTAT_CLR8_SHIFT (0x00000009u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_EVSTAT_CLR8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX8_RSTMUX_LOCK8_MASK (0x00000001u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_LOCK8_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_LOCK8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX8_RSTMUX_OMODE8_MASK (0x0000000Eu)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_OMODE8_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_OMODE8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX8_RESETVAL (0x00000080u)

/* rstmux9 */

#define CSL_BOOTCFG_RSTMUX9_RSTMUX_DELAY9_MASK (0x000000E0u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_DELAY9_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_DELAY9_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_RSTMUX9_RSTMUX_EVSTAT9_MASK (0x00000010u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_EVSTAT9_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_EVSTAT9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX9_RSTMUX_EVSTAT_CLR9_MASK (0x00000200u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_EVSTAT_CLR9_SHIFT (0x00000009u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_EVSTAT_CLR9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX9_RSTMUX_LOCK9_MASK (0x00000001u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_LOCK9_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_LOCK9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX9_RSTMUX_OMODE9_MASK (0x0000000Eu)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_OMODE9_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_OMODE9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX9_RESETVAL (0x00000080u)

/* rstmux10 */

#define CSL_BOOTCFG_RSTMUX10_RSTMUX_DELAY10_MASK (0x000000E0u)
#define CSL_BOOTCFG_RSTMUX10_RSTMUX_DELAY10_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RSTMUX10_RSTMUX_DELAY10_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_RSTMUX10_RSTMUX_EVSTAT10_MASK (0x00000010u)
#define CSL_BOOTCFG_RSTMUX10_RSTMUX_EVSTAT10_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RSTMUX10_RSTMUX_EVSTAT10_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX10_RSTMUX_EVSTAT_CLR10_MASK (0x00000200u)
#define CSL_BOOTCFG_RSTMUX10_RSTMUX_EVSTAT_CLR10_SHIFT (0x00000009u)
#define CSL_BOOTCFG_RSTMUX10_RSTMUX_EVSTAT_CLR10_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX10_RSTMUX_LOCK10_MASK (0x00000001u)
#define CSL_BOOTCFG_RSTMUX10_RSTMUX_LOCK10_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RSTMUX10_RSTMUX_LOCK10_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX10_RSTMUX_OMODE10_MASK (0x0000000Eu)
#define CSL_BOOTCFG_RSTMUX10_RSTMUX_OMODE10_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RSTMUX10_RSTMUX_OMODE10_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX10_RESETVAL (0x00000080u)

/* rstmux11 */

#define CSL_BOOTCFG_RSTMUX11_RSTMUX_DELAY11_MASK (0x000000E0u)
#define CSL_BOOTCFG_RSTMUX11_RSTMUX_DELAY11_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RSTMUX11_RSTMUX_DELAY11_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_RSTMUX11_RSTMUX_EVSTAT11_MASK (0x00000010u)
#define CSL_BOOTCFG_RSTMUX11_RSTMUX_EVSTAT11_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RSTMUX11_RSTMUX_EVSTAT11_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX11_RSTMUX_EVSTAT_CLR11_MASK (0x00000200u)
#define CSL_BOOTCFG_RSTMUX11_RSTMUX_EVSTAT_CLR11_SHIFT (0x00000009u)
#define CSL_BOOTCFG_RSTMUX11_RSTMUX_EVSTAT_CLR11_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX11_RSTMUX_LOCK11_MASK (0x00000001u)
#define CSL_BOOTCFG_RSTMUX11_RSTMUX_LOCK11_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RSTMUX11_RSTMUX_LOCK11_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX11_RSTMUX_OMODE11_MASK (0x0000000Eu)
#define CSL_BOOTCFG_RSTMUX11_RSTMUX_OMODE11_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RSTMUX11_RSTMUX_OMODE11_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX11_RESETVAL (0x00000080u)

/* main_pll_ctl0 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLD_MASK                     (0x0000003FU)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLD_SHIFT                    (0U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLD_RESETVAL                 (0x00000000U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLD_MAX                      (0x0000003fU)

#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLM_MASK                     (0x0007F000U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLM_SHIFT                    (12U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLM_RESETVAL                 (0x00000000U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLM_MAX                      (0x0000007fU)

#define CSL_BOOTCFG_MAIN_PLL_CTL0_BWADJ_MASK                    (0xFF000000U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_BWADJ_SHIFT                   (24U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_BWADJ_RESETVAL                (0x00000005U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_BWADJ_MAX                     (0x000000ffU)
#endif

#define CSL_BOOTCFG_MAIN_PLL_CTL0_MAIN_PLL_CTL0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_MAIN_PLL_CTL0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_MAIN_PLL_CTL0_RESETVAL (0x05000000u)

#define CSL_BOOTCFG_MAIN_PLL_CTL0_RESETVAL (0x05000000u)

/* main_pll_ctl1 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_MAIN_PLL_CTL1_BWADJ_MASK                    (0x0000000FU)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_BWADJ_SHIFT                   (0U)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_BWADJ_RESETVAL                (0x00000000U)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_BWADJ_MAX                     (0x0000000fU)

#define CSL_BOOTCFG_MAIN_PLL_CTL1_ENSAT_MASK                    (0x00000040U)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_ENSAT_SHIFT                   (6U)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_ENSAT_RESETVAL                (0x00000001U)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_ENSAT_MAX                     (0x00000001U)
#endif

#define CSL_BOOTCFG_MAIN_PLL_CTL1_MAIN_PLL_CTL1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_MAIN_PLL_CTL1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_MAIN_PLL_CTL1_RESETVAL (0x00000040u)

#define CSL_BOOTCFG_MAIN_PLL_CTL1_RESETVAL (0x00000040u)

/* pass_pll_ctl0 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLD_MASK                     (0x0000003FU)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLD_SHIFT                    (0U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLD_RESETVAL                 (0x00000000U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLD_MAX                      (0x0000003fU)

#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLM_MASK                     (0x0007FFC0U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLM_SHIFT                    (6U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLM_RESETVAL                 (0x00000013U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLM_MAX                      (0x00001fffU)

#define CSL_BOOTCFG_PASS_PLL_CTL0_CLKOD_MASK                    (0x00780000U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_CLKOD_SHIFT                   (19U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_CLKOD_RESETVAL                (0x00000001U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_CLKOD_MAX                     (0x0000000fU)

#define CSL_BOOTCFG_PASS_PLL_CTL0_BYPASS_MASK                    (0x00800000U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_BYPASS_SHIFT                   (23U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_BYPASS_RESETVAL                (0x00000001U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_BYPASS_MAX                     (0x00000001U)

#define CSL_BOOTCFG_PASS_PLL_CTL0_BWADJ_MASK                     (0xFF000000U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_BWADJ_SHIFT                    (24U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_BWADJ_RESETVAL                 (0x00000009U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_BWADJ_MAX                      (0x000000ffU)
#endif

#define CSL_BOOTCFG_PASS_PLL_CTL0_PA_PLL_CTL0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PA_PLL_CTL0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PA_PLL_CTL0_RESETVAL (0x098804C0u)

#define CSL_BOOTCFG_PASS_PLL_CTL0_RESETVAL (0x098804C0u)

/* pass_pll_ctl1 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_PASS_PLL_CTL1_BWADJ_MASK                    (0x0000000FU)
#define CSL_BOOTCFG_PASS_PLL_CTL1_BWADJ_SHIFT                   (0U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_BWADJ_RESETVAL                (0x00000000U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_BWADJ_MAX                     (0x0000000fU)

#define CSL_BOOTCFG_PASS_PLL_CTL1_ENSAT_MASK                    (0x00000040U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_ENSAT_SHIFT                   (6U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_ENSAT_RESETVAL                (0x00000001U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_ENSAT_MAX                     (0x00000001U)

#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLSEL_MASK                   (0x00002000U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLSEL_SHIFT                  (13U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLSEL_RESETVAL               (0x00000000U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLSEL_MAX                    (0x00000001U)

#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLRST_MASK                   (0x00004000U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLRST_SHIFT                  (14U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLRST_RESETVAL               (0x00000000U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLRST_MAX                    (0x00000001U)
#endif

#define CSL_BOOTCFG_PASS_PLL_CTL1_PA_PLL_CTL1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PA_PLL_CTL1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PA_PLL_CTL1_RESETVAL (0x00000040u)

#define CSL_BOOTCFG_PASS_PLL_CTL1_RESETVAL (0x00000040u)

/* ddr3a_pll_ctl0 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLD_MASK                    (0x0000003FU)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLD_SHIFT                   (0U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLD_RESETVAL                (0x00000000U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLD_MAX                     (0x0000003fU)

#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLM_MASK                    (0x0007FFC0U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLM_SHIFT                   (6U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLM_RESETVAL                (0x00000013U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLM_MAX                     (0x00001fffU)

#define CSL_BOOTCFG_DDR3A_PLL_CTL0_CLKOD_MASK                   (0x00780000U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_CLKOD_SHIFT                  (19U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_CLKOD_RESETVAL               (0x00000001U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_CLKOD_MAX                    (0x0000000fU)

#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BYPASS_MASK                  (0x00800000U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BYPASS_SHIFT                 (23U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BYPASS_RESETVAL              (0x00000001U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BYPASS_MAX                   (0x00000001U)

#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BWADJ_MASK                   (0xFF000000U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BWADJ_SHIFT                  (24U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BWADJ_RESETVAL               (0x00000009U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BWADJ_MAX                    (0x000000ffU)
#endif

#define CSL_BOOTCFG_DDR3A_PLL_CTL0_DDR3A_PLL_CTL0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_DDR3A_PLL_CTL0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_DDR3A_PLL_CTL0_RESETVAL (0x098804C0u)

#define CSL_BOOTCFG_DDR3A_PLL_CTL0_RESETVAL (0x098804C0u)

/* ddr3a_pll_ctl1 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_BWADJ_MASK                   (0x0000000FU)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_BWADJ_SHIFT                  (0U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_BWADJ_RESETVAL               (0x00000000U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_BWADJ_MAX                    (0x0000000fU)

#define CSL_BOOTCFG_DDR3A_PLL_CTL1_ENSAT_MASK                   (0x00000040U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_ENSAT_SHIFT                  (6U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_ENSAT_RESETVAL               (0x00000001U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_ENSAT_MAX                    (0x00000001U)

#define CSL_BOOTCFG_DDR3A_PLL_CTL1_PLLRST_MASK                  (0x00004000U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_PLLRST_SHIFT                 (14U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_PLLRST_RESETVAL              (0x00000000U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_PLLRST_MAX                   (0x00000001U)
#endif

#define CSL_BOOTCFG_DDR3A_PLL_CTL1_DDR3A_PLL_CTL1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_DDR3A_PLL_CTL1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_DDR3A_PLL_CTL1_RESETVAL (0x00000040u)

#define CSL_BOOTCFG_DDR3A_PLL_CTL1_RESETVAL (0x00000040u)

/* ddr3b_pll_ctl0 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_DDR3B_PLL_CTL0_PLLD_MASK                    (0x0000003FU)
#define CSL_BOOTCFG_DDR3B_PLL_CTL0_PLLD_SHIFT                   (0U)
#define CSL_BOOTCFG_DDR3B_PLL_CTL0_PLLD_RESETVAL                (0x00000000U)
#define CSL_BOOTCFG_DDR3B_PLL_CTL0_PLLD_MAX                     (0x0000003fU)

#define CSL_BOOTCFG_DDR3B_PLL_CTL0_PLLM_MASK                    (0x0007FFC0U)
#define CSL_BOOTCFG_DDR3B_PLL_CTL0_PLLM_SHIFT                   (6U)
#define CSL_BOOTCFG_DDR3B_PLL_CTL0_PLLM_RESETVAL                (0x00000013U)
#define CSL_BOOTCFG_DDR3B_PLL_CTL0_PLLM_MAX                     (0x00001fffU)

#define CSL_BOOTCFG_DDR3B_PLL_CTL0_CLKOD_MASK                   (0x00780000U)
#define CSL_BOOTCFG_DDR3B_PLL_CTL0_CLKOD_SHIFT                  (19U)
#define CSL_BOOTCFG_DDR3B_PLL_CTL0_CLKOD_RESETVAL               (0x00000001U)
#define CSL_BOOTCFG_DDR3B_PLL_CTL0_CLKOD_MAX                    (0x0000000fU)

#define CSL_BOOTCFG_DDR3B_PLL_CTL0_BYPASS_MASK                  (0x00800000U)
#define CSL_BOOTCFG_DDR3B_PLL_CTL0_BYPASS_SHIFT                 (23U)
#define CSL_BOOTCFG_DDR3B_PLL_CTL0_BYPASS_RESETVAL              (0x00000001U)
#define CSL_BOOTCFG_DDR3B_PLL_CTL0_BYPASS_MAX                   (0x00000001U)

#define CSL_BOOTCFG_DDR3B_PLL_CTL0_BWADJ_MASK                   (0xFF000000U)
#define CSL_BOOTCFG_DDR3B_PLL_CTL0_BWADJ_SHIFT                  (24U)
#define CSL_BOOTCFG_DDR3B_PLL_CTL0_BWADJ_RESETVAL               (0x00000009U)
#define CSL_BOOTCFG_DDR3B_PLL_CTL0_BWADJ_MAX                    (0x000000ffU)
#endif

#define CSL_BOOTCFG_DDR3B_PLL_CTL0_DDR3B_PLL_CTL0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DDR3B_PLL_CTL0_DDR3B_PLL_CTL0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DDR3B_PLL_CTL0_DDR3B_PLL_CTL0_RESETVAL (0x098804C0u)

#define CSL_BOOTCFG_DDR3B_PLL_CTL0_RESETVAL (0x098804C0u)

/* ddr3b_pll_ctl1 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_DDR3B_PLL_CTL1_BWADJ_MASK                   (0x0000000FU)
#define CSL_BOOTCFG_DDR3B_PLL_CTL1_BWADJ_SHIFT                  (0U)
#define CSL_BOOTCFG_DDR3B_PLL_CTL1_BWADJ_RESETVAL               (0x00000000U)
#define CSL_BOOTCFG_DDR3B_PLL_CTL1_BWADJ_MAX                    (0x0000000fU)

#define CSL_BOOTCFG_DDR3B_PLL_CTL1_ENSAT_MASK                   (0x00000040U)
#define CSL_BOOTCFG_DDR3B_PLL_CTL1_ENSAT_SHIFT                  (6U)
#define CSL_BOOTCFG_DDR3B_PLL_CTL1_ENSAT_RESETVAL               (0x00000001U)
#define CSL_BOOTCFG_DDR3B_PLL_CTL1_ENSAT_MAX                    (0x00000001U)

#define CSL_BOOTCFG_DDR3B_PLL_CTL1_PLLRST_MASK                  (0x00004000U)
#define CSL_BOOTCFG_DDR3B_PLL_CTL1_PLLRST_SHIFT                 (14U)
#define CSL_BOOTCFG_DDR3B_PLL_CTL1_PLLRST_RESETVAL              (0x00000000U)
#define CSL_BOOTCFG_DDR3B_PLL_CTL1_PLLRST_MAX                   (0x00000001U)
#endif

#define CSL_BOOTCFG_DDR3B_PLL_CTL1_DDR3B_PLL_CTL1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DDR3B_PLL_CTL1_DDR3B_PLL_CTL1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DDR3B_PLL_CTL1_DDR3B_PLL_CTL1_RESETVAL (0x00000040u)

#define CSL_BOOTCFG_DDR3B_PLL_CTL1_RESETVAL (0x00000040u)

/* arm_pll_ctl0 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_ARM_PLL_CTL0_PLLD_MASK                      (0x0000003FU)
#define CSL_BOOTCFG_ARM_PLL_CTL0_PLLD_SHIFT                     (0U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_PLLD_RESETVAL                  (0x00000000U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_PLLD_MAX                       (0x0000003fU)

#define CSL_BOOTCFG_ARM_PLL_CTL0_PLLM_MASK                      (0x0007FFC0U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_PLLM_SHIFT                     (6U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_PLLM_RESETVAL                  (0x00000013U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_PLLM_MAX                       (0x00001fffU)

#define CSL_BOOTCFG_ARM_PLL_CTL0_CLKOD_MASK                     (0x00780000U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_CLKOD_SHIFT                    (19U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_CLKOD_RESETVAL                 (0x00000001U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_CLKOD_MAX                      (0x0000000fU)

#define CSL_BOOTCFG_ARM_PLL_CTL0_BYPASS_MASK                    (0x00800000U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_BYPASS_SHIFT                   (23U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_BYPASS_RESETVAL                (0x00000001U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_BYPASS_MAX                     (0x00000001U)

#define CSL_BOOTCFG_ARM_PLL_CTL0_BWADJ_MASK                     (0xFF000000U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_BWADJ_SHIFT                    (24U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_BWADJ_RESETVAL                 (0x00000009U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_BWADJ_MAX                      (0x000000ffU)
#endif

#define CSL_BOOTCFG_ARM_PLL_CTL0_ARM_PLL_CTL0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARM_PLL_CTL0_ARM_PLL_CTL0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_PLL_CTL0_ARM_PLL_CTL0_RESETVAL (0x098804C0u)

#define CSL_BOOTCFG_ARM_PLL_CTL0_RESETVAL (0x098804C0u)

/* arm_pll_ctl1 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_ARM_PLL_CTL1_BWADJ_MASK                     (0x0000000FU)
#define CSL_BOOTCFG_ARM_PLL_CTL1_BWADJ_SHIFT                    (0U)
#define CSL_BOOTCFG_ARM_PLL_CTL1_BWADJ_RESETVAL                 (0x00000000U)
#define CSL_BOOTCFG_ARM_PLL_CTL1_BWADJ_MAX                      (0x0000000fU)

#define CSL_BOOTCFG_ARM_PLL_CTL1_ENSAT_MASK                     (0x00000040U)
#define CSL_BOOTCFG_ARM_PLL_CTL1_ENSAT_SHIFT                    (6U)
#define CSL_BOOTCFG_ARM_PLL_CTL1_ENSAT_RESETVAL                 (0x00000001U)
#define CSL_BOOTCFG_ARM_PLL_CTL1_ENSAT_MAX                      (0x00000001U)

#define CSL_BOOTCFG_ARM_PLL_CTL1_PLLRST_MASK                    (0x00004000U)
#define CSL_BOOTCFG_ARM_PLL_CTL1_PLLRST_SHIFT                   (14U)
#define CSL_BOOTCFG_ARM_PLL_CTL1_PLLRST_RESETVAL                (0x00000000U)
#define CSL_BOOTCFG_ARM_PLL_CTL1_PLLRST_MAX
#endif

#define CSL_BOOTCFG_ARM_PLL_CTL1_ARM_PLL_CTL1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARM_PLL_CTL1_ARM_PLL_CTL1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_PLL_CTL1_ARM_PLL_CTL1_RESETVAL (0x00000040u)

#define CSL_BOOTCFG_ARM_PLL_CTL1_RESETVAL (0x00000040u)

/* secure_control */

#define CSL_BOOTCFG_SECURE_CONTROL_PBIST_SECURE_EN_MASK (0x00000001u)
#define CSL_BOOTCFG_SECURE_CONTROL_PBIST_SECURE_EN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SECURE_CONTROL_PBIST_SECURE_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SECURE_CONTROL_VUSR_SEC_EN_MASK (0x00000002u)
#define CSL_BOOTCFG_SECURE_CONTROL_VUSR_SEC_EN_SHIFT (0x00000001u)
#define CSL_BOOTCFG_SECURE_CONTROL_VUSR_SEC_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SECURE_CONTROL_RESETVAL (0x00000000u)

/* arm_endian_cfg0_0 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_0_ARM_ENDIAN_CFG0_ADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_0_ARM_ENDIAN_CFG0_ADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_0_ARM_ENDIAN_CFG0_ADDR_RESETVAL (0x000001C0u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_0_RESETVAL (0x0001C000u)

/* arm_endian_cfg0_1 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_1_ARM_ENDIAN_CFG0_SIZE_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_1_ARM_ENDIAN_CFG0_SIZE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_1_ARM_ENDIAN_CFG0_SIZE_RESETVAL (0x00000006u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_1_RESETVAL (0x00000006u)

/* arm_endian_cfg0_2 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_2_ARM_ENDIAN_CFG0_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_2_ARM_ENDIAN_CFG0_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_2_ARM_ENDIAN_CFG0_DIS_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_2_RESETVAL (0x00000001u)

/* arm_endian_cfg1_0 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_0_ARM_ENDIAN_CFG1_ADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_0_ARM_ENDIAN_CFG1_ADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_0_ARM_ENDIAN_CFG1_ADDR_RESETVAL (0x00000200u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_0_RESETVAL (0x00020000u)

/* arm_endian_cfg1_1 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_1_ARM_ENDIAN_CFG1_SIZE_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_1_ARM_ENDIAN_CFG1_SIZE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_1_ARM_ENDIAN_CFG1_SIZE_RESETVAL (0x00000009u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_1_RESETVAL (0x00000009u)

/* arm_endian_cfg1_2 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_2_ARM_ENDIAN_CFG1_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_2_ARM_ENDIAN_CFG1_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_2_ARM_ENDIAN_CFG1_DIS_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_2_RESETVAL (0x00000001u)

/* arm_endian_cfg2_0 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_0_ARM_ENDIAN_CFG2_ADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_0_ARM_ENDIAN_CFG2_ADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_0_ARM_ENDIAN_CFG2_ADDR_RESETVAL (0x00000BC0u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_0_RESETVAL (0x000BC000u)

/* arm_endian_cfg2_1 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_1_ARM_ENDIAN_CFG2_SIZE_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_1_ARM_ENDIAN_CFG2_SIZE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_1_ARM_ENDIAN_CFG2_SIZE_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_1_RESETVAL (0x00000004u)

/* arm_endian_cfg2_2 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_2_ARM_ENDIAN_CFG2_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_2_ARM_ENDIAN_CFG2_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_2_ARM_ENDIAN_CFG2_DIS_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_2_RESETVAL (0x00000001u)

/* arm_endian_cfg3_0 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_0_ARM_ENDIAN_CFG3_ADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_0_ARM_ENDIAN_CFG3_ADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_0_ARM_ENDIAN_CFG3_ADDR_RESETVAL (0x00002100u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_0_RESETVAL (0x00210000u)

/* arm_endian_cfg3_1 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_1_ARM_ENDIAN_CFG3_SIZE_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_1_ARM_ENDIAN_CFG3_SIZE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_1_ARM_ENDIAN_CFG3_SIZE_RESETVAL (0x00000008u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_1_RESETVAL (0x00000008u)

/* arm_endian_cfg3_2 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_2_ARM_ENDIAN_CFG3_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_2_ARM_ENDIAN_CFG3_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_2_ARM_ENDIAN_CFG3_DIS_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_2_RESETVAL (0x00000001u)

/* arm_endian_cfg4_0 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_0_ARM_ENDIAN_CFG4_ADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_0_ARM_ENDIAN_CFG4_ADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_0_ARM_ENDIAN_CFG4_ADDR_RESETVAL (0x0000023Au)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_0_RESETVAL (0x00023A00u)

/* arm_endian_cfg4_1 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_1_ARM_ENDIAN_CFG4_SIZE_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_1_ARM_ENDIAN_CFG4_SIZE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_1_ARM_ENDIAN_CFG4_SIZE_RESETVAL (0x00000005u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_1_RESETVAL (0x00000005u)

/* arm_endian_cfg4_2 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_2_ARM_ENDIAN_CFG4_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_2_ARM_ENDIAN_CFG4_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_2_ARM_ENDIAN_CFG4_DIS_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_2_RESETVAL (0x00000001u)

/* arm_endian_cfg5_0 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_0_ARM_ENDIAN_CFG5_ADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_0_ARM_ENDIAN_CFG5_ADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_0_ARM_ENDIAN_CFG5_ADDR_RESETVAL (0x00002400u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_0_RESETVAL (0x00240000u)

/* arm_endian_cfg5_1 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_1_ARM_ENDIAN_CFG5_SIZE_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_1_ARM_ENDIAN_CFG5_SIZE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_1_ARM_ENDIAN_CFG5_SIZE_RESETVAL (0x00000006u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_1_RESETVAL (0x00000006u)

/* armendian_cfg5_2 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_2_ARM_ENDIAN_CFG5_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_2_ARM_ENDIAN_CFG5_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_2_ARM_ENDIAN_CFG5_DIS_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_2_RESETVAL (0x00000001u)

/* armendian_cfg6_0 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_0_ARM_ENDIAN_CFG6_ADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_0_ARM_ENDIAN_CFG6_ADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_0_ARM_ENDIAN_CFG6_ADDR_RESETVAL (0x00010000u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_0_RESETVAL (0x01000000u)

/* armendian_cfg6_1 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_1_ARM_ENDIAN_CFG6_SIZE_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_1_ARM_ENDIAN_CFG6_SIZE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_1_ARM_ENDIAN_CFG6_SIZE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_1_RESETVAL (0x00000000u)

/* armendian_cfg6_2 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_2_ARM_ENDIAN_CFG6_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_2_ARM_ENDIAN_CFG6_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_2_ARM_ENDIAN_CFG6_DIS_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_2_RESETVAL (0x00000001u)

/* armendian_cfg7_0 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_0_ARM_ENDIAN_CFG7_ADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_0_ARM_ENDIAN_CFG7_ADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_0_ARM_ENDIAN_CFG7_ADDR_RESETVAL (0x00FFFFFFu)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_0_RESETVAL (0xFFFFFF00u)

/* armendian_cfg7_1 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_1_ARM_ENDIAN_CFG7_SIZE_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_1_ARM_ENDIAN_CFG7_SIZE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_1_ARM_ENDIAN_CFG7_SIZE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_1_RESETVAL (0x00000000u)

/* armendian_cfg7_2 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_2_ARM_ENDIAN_CFG7_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_2_ARM_ENDIAN_CFG7_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_2_ARM_ENDIAN_CFG7_DIS_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_2_RESETVAL (0x00000001u)

/* class0_efuse1_reg */

#define CSL_BOOTCFG_CLASS0_EFUSE1_REG_CLASS0_EFUSE1_REG_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_CLASS0_EFUSE1_REG_CLASS0_EFUSE1_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_CLASS0_EFUSE1_REG_CLASS0_EFUSE1_REG_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CLASS0_EFUSE1_REG_RESETVAL (0x00000000u)

/* efuse1_reg0 */

#define CSL_BOOTCFG_EFUSE1_REG0_EFUSE1_REG0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE1_REG0_EFUSE1_REG0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE1_REG0_EFUSE1_REG0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE1_REG0_RESETVAL (0x00000000u)

/* efuse1_reg1 */

#define CSL_BOOTCFG_EFUSE1_REG1_EFUSE1_REG1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE1_REG1_EFUSE1_REG1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE1_REG1_EFUSE1_REG1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE1_REG1_RESETVAL (0x00000000u)

/* efuse1_reg2 */

#define CSL_BOOTCFG_EFUSE1_REG2_EFUSE1_REG2_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE1_REG2_EFUSE1_REG2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE1_REG2_EFUSE1_REG2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE1_REG2_RESETVAL (0x00000000u)

/* efuse1_reg3 */

#define CSL_BOOTCFG_EFUSE1_REG3_EFUSE1_REG3_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE1_REG3_EFUSE1_REG3_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE1_REG3_EFUSE1_REG3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE1_REG3_RESETVAL (0x00000000u)

/* efuse1_reg4 */

#define CSL_BOOTCFG_EFUSE1_REG4_EFUSE1_REG4_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE1_REG4_EFUSE1_REG4_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE1_REG4_EFUSE1_REG4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE1_REG4_RESETVAL (0x00000000u)

/* efuse1_reg5 */

#define CSL_BOOTCFG_EFUSE1_REG5_EFUSE1_REG5_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE1_REG5_EFUSE1_REG5_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE1_REG5_EFUSE1_REG5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE1_REG5_RESETVAL (0x00000000u)

/* efuse1_reg6 */

#define CSL_BOOTCFG_EFUSE1_REG6_EFUSE1_REG6_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE1_REG6_EFUSE1_REG6_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE1_REG6_EFUSE1_REG6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE1_REG6_RESETVAL (0x00000000u)

/* efuse1_reg7 */

#define CSL_BOOTCFG_EFUSE1_REG7_EFUSE1_REG7_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE1_REG7_EFUSE1_REG7_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE1_REG7_EFUSE1_REG7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE1_REG7_RESETVAL (0x00000000u)

/* efuse1_reg8 */

#define CSL_BOOTCFG_EFUSE1_REG8_EFUSE1_REG8_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE1_REG8_EFUSE1_REG8_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE1_REG8_EFUSE1_REG8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE1_REG8_RESETVAL (0x00000000u)

/* efuse1_reg9 */

#define CSL_BOOTCFG_EFUSE1_REG9_EFUSE1_REG9_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE1_REG9_EFUSE1_REG9_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE1_REG9_EFUSE1_REG9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE1_REG9_RESETVAL (0x00000000u)

/* efuse1_reg10 */

#define CSL_BOOTCFG_EFUSE1_REG10_EFUSE1_REG10_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE1_REG10_EFUSE1_REG10_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE1_REG10_EFUSE1_REG10_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE1_REG10_RESETVAL (0x00000000u)

/* efuse1_reg11 */

#define CSL_BOOTCFG_EFUSE1_REG11_EFUSE1_REG11_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE1_REG11_EFUSE1_REG11_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE1_REG11_EFUSE1_REG11_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE1_REG11_RESETVAL (0x00000000u)

/* efuse1_reg12 */

#define CSL_BOOTCFG_EFUSE1_REG12_EFUSE1_REG12_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE1_REG12_EFUSE1_REG12_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE1_REG12_EFUSE1_REG12_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE1_REG12_RESETVAL (0x00000000u)

/* efuse1_reg13 */

#define CSL_BOOTCFG_EFUSE1_REG13_EFUSE1_REG13_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE1_REG13_EFUSE1_REG13_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE1_REG13_EFUSE1_REG13_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE1_REG13_RESETVAL (0x00000000u)

/* efuse1_reg14 */

#define CSL_BOOTCFG_EFUSE1_REG14_EFUSE1_REG14_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE1_REG14_EFUSE1_REG14_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE1_REG14_EFUSE1_REG14_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE1_REG14_RESETVAL (0x00000000u)

/* efuse1_reg15 */

#define CSL_BOOTCFG_EFUSE1_REG15_EFUSE1_REG15_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE1_REG15_EFUSE1_REG15_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE1_REG15_EFUSE1_REG15_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE1_REG15_RESETVAL (0x00000000u)

/* chip_misc */

#define CSL_BOOTCFG_CHIP_MISC_AET_MUX_SEL0_MASK (0x00010000u)
#define CSL_BOOTCFG_CHIP_MISC_AET_MUX_SEL0_SHIFT (0x00000010u)
#define CSL_BOOTCFG_CHIP_MISC_AET_MUX_SEL0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_AET_MUX_SEL1_MASK (0x00020000u)
#define CSL_BOOTCFG_CHIP_MISC_AET_MUX_SEL1_SHIFT (0x00000011u)
#define CSL_BOOTCFG_CHIP_MISC_AET_MUX_SEL1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_MSMC_BLOCK_PARITY_RST_MASK (0x00001000u)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_MSMC_BLOCK_PARITY_RST_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_MSMC_BLOCK_PARITY_RST_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_QM_PRI_MASK (0x00000007u)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_QM_PRI_SHIFT (0x00000000u)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_QM_PRI_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_EFUSE_ACTUAL_EN_MASK (0x08000000u)
#define CSL_BOOTCFG_CHIP_MISC_EFUSE_ACTUAL_EN_SHIFT (0x0000001Bu)
#define CSL_BOOTCFG_CHIP_MISC_EFUSE_ACTUAL_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_EFUSE_REDUND_EN_MASK (0x04000000u)
#define CSL_BOOTCFG_CHIP_MISC_EFUSE_REDUND_EN_SHIFT (0x0000001Au)
#define CSL_BOOTCFG_CHIP_MISC_EFUSE_REDUND_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_RACAB_DISABLE_MASK (0x00002000u)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_RACAB_DISABLE_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_RACAB_DISABLE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_RACCD_DISABLE_MASK (0x00004000u)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_RACCD_DISABLE_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_RACCD_DISABLE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_RST_ISO_IP_RST_BLK_MASK (0x03F80000u)
#define CSL_BOOTCFG_CHIP_MISC_RST_ISO_IP_RST_BLK_SHIFT (0x00000013u)
#define CSL_BOOTCFG_CHIP_MISC_RST_ISO_IP_RST_BLK_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_USB_PME_EN_MASK (0x00040000u)
#define CSL_BOOTCFG_CHIP_MISC_USB_PME_EN_SHIFT (0x00000012u)
#define CSL_BOOTCFG_CHIP_MISC_USB_PME_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_RESETVAL (0x00006000u)

/* sr_pinctl */

#define CSL_BOOTCFG_SR_PINCTL_PROC1_VCL_VD_OFF_MASK (0x00000002u)
#define CSL_BOOTCFG_SR_PINCTL_PROC1_VCL_VD_OFF_SHIFT (0x00000001u)
#define CSL_BOOTCFG_SR_PINCTL_PROC1_VCL_VD_OFF_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SR_PINCTL_PROC1_VCNTL1_0_OFF_MASK (0x00000001u)
#define CSL_BOOTCFG_SR_PINCTL_PROC1_VCNTL1_0_OFF_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SR_PINCTL_PROC1_VCNTL1_0_OFF_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SR_PINCTL_PROC2_VCL_VD_OFF_MASK (0x00000004u)
#define CSL_BOOTCFG_SR_PINCTL_PROC2_VCL_VD_OFF_SHIFT (0x00000002u)
#define CSL_BOOTCFG_SR_PINCTL_PROC2_VCL_VD_OFF_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SR_PINCTL_RESETVAL (0x00000000u)

/* spare0 */

#define CSL_BOOTCFG_SPARE0_SPARE0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SPARE0_SPARE0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SPARE0_SPARE0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE0_RESETVAL   (0x00000000u)

/* spare1 */

#define CSL_BOOTCFG_SPARE1_SPARE1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SPARE1_SPARE1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SPARE1_SPARE1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE1_RESETVAL   (0x00000000u)

/* sys_endian */

#define CSL_BOOTCFG_SYS_ENDIAN_SYS_ENDIAN_MASK (0x00000001u)
#define CSL_BOOTCFG_SYS_ENDIAN_SYS_ENDIAN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SYS_ENDIAN_SYS_ENDIAN_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_SYS_ENDIAN_RESETVAL (0x00000001u)

/* synce_pinctl */

#define CSL_BOOTCFG_SYNCE_PINCTL_SYNCE_PINCTL_MASK (0x000000FFu)
#define CSL_BOOTCFG_SYNCE_PINCTL_SYNCE_PINCTL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SYNCE_PINCTL_SYNCE_PINCTL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SYNCE_PINCTL_RESETVAL (0x00000000u)

/* margin3 */

#define CSL_BOOTCFG_MARGIN3_DFTREAD1_MASK (0x00FFFFFFu)
#define CSL_BOOTCFG_MARGIN3_DFTREAD1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_MARGIN3_DFTREAD1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MARGIN3_RESETVAL  (0x00000000u)

/* usb_reg0 */

#define CSL_BOOTCFG_USB_REG0_USB_PHY_RTUNE_ACK_MASK (0x00000800u)
#define CSL_BOOTCFG_USB_REG0_USB_PHY_RTUNE_ACK_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_USB_REG0_USB_PHY_RTUNE_ACK_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG0_USB_PHY_RTUNE_REQ_MASK (0x00000400u)
#define CSL_BOOTCFG_USB_REG0_USB_PHY_RTUNE_REQ_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_USB_REG0_USB_PHY_RTUNE_REQ_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG0_USB_PHY_TC_LOOPBACKENB_MASK (0x00000010u)
#define CSL_BOOTCFG_USB_REG0_USB_PHY_TC_LOOPBACKENB_SHIFT (0x00000004u)
#define CSL_BOOTCFG_USB_REG0_USB_PHY_TC_LOOPBACKENB_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG0_USB_PHY_TC_TEST_POWERDOWN_HSP_MASK (0x00000020u)
#define CSL_BOOTCFG_USB_REG0_USB_PHY_TC_TEST_POWERDOWN_HSP_SHIFT (0x00000005u)
#define CSL_BOOTCFG_USB_REG0_USB_PHY_TC_TEST_POWERDOWN_HSP_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG0_USB_PHY_TC_TEST_POWERDOWN_SSP_MASK (0x00000040u)
#define CSL_BOOTCFG_USB_REG0_USB_PHY_TC_TEST_POWERDOWN_SSP_SHIFT (0x00000006u)
#define CSL_BOOTCFG_USB_REG0_USB_PHY_TC_TEST_POWERDOWN_SSP_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG0_USB_PHY_TC_VATESTENB_MASK (0x00000180u)
#define CSL_BOOTCFG_USB_REG0_USB_PHY_TC_VATESTENB_SHIFT (0x00000007u)
#define CSL_BOOTCFG_USB_REG0_USB_PHY_TC_VATESTENB_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG0_USB_UTMI_TXBITSTUFFEN_MASK (0x00000001u)
#define CSL_BOOTCFG_USB_REG0_USB_UTMI_TXBITSTUFFEN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_USB_REG0_USB_UTMI_TXBITSTUFFEN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG0_USB_UTMI_TXBITSTUFFENH_MASK (0x00000002u)
#define CSL_BOOTCFG_USB_REG0_USB_UTMI_TXBITSTUFFENH_SHIFT (0x00000001u)
#define CSL_BOOTCFG_USB_REG0_USB_UTMI_TXBITSTUFFENH_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG0_USB_UTMI_VBUSVLDEXT_MASK (0x00000004u)
#define CSL_BOOTCFG_USB_REG0_USB_UTMI_VBUSVLDEXT_SHIFT (0x00000002u)
#define CSL_BOOTCFG_USB_REG0_USB_UTMI_VBUSVLDEXT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG0_USB_UTMI_WORDINTERFACE_MASK (0x00000008u)
#define CSL_BOOTCFG_USB_REG0_USB_UTMI_WORDINTERFACE_SHIFT (0x00000003u)
#define CSL_BOOTCFG_USB_REG0_USB_UTMI_WORDINTERFACE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG0_RESETVAL (0x00000000u)

/* usb_reg1 */

#define CSL_BOOTCFG_USB_REG1_USB_PIPE_ALT_CLK_EN_MASK (0x00000001u)
#define CSL_BOOTCFG_USB_REG1_USB_PIPE_ALT_CLK_EN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_USB_REG1_USB_PIPE_ALT_CLK_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG1_USB_PIPE_ALT_CLK_REQ_MASK (0x00000002u)
#define CSL_BOOTCFG_USB_REG1_USB_PIPE_ALT_CLK_REQ_SHIFT (0x00000001u)
#define CSL_BOOTCFG_USB_REG1_USB_PIPE_ALT_CLK_REQ_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG1_USB_PIPE_ALT_CLK_SEL_MASK (0x00000004u)
#define CSL_BOOTCFG_USB_REG1_USB_PIPE_ALT_CLK_SEL_SHIFT (0x00000002u)
#define CSL_BOOTCFG_USB_REG1_USB_PIPE_ALT_CLK_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG1_USB_PIPE_EXT_PCLK_REQ_MASK (0x00000008u)
#define CSL_BOOTCFG_USB_REG1_USB_PIPE_EXT_PCLK_REQ_SHIFT (0x00000003u)
#define CSL_BOOTCFG_USB_REG1_USB_PIPE_EXT_PCLK_REQ_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG1_USB_PIPE_REF_CLKREQ_N_MASK (0x00000020u)
#define CSL_BOOTCFG_USB_REG1_USB_PIPE_REF_CLKREQ_N_SHIFT (0x00000005u)
#define CSL_BOOTCFG_USB_REG1_USB_PIPE_REF_CLKREQ_N_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG1_USB_PIPE_TX2RX_LOOPBK_MASK (0x00000010u)
#define CSL_BOOTCFG_USB_REG1_USB_PIPE_TX2RX_LOOPBK_SHIFT (0x00000004u)
#define CSL_BOOTCFG_USB_REG1_USB_PIPE_TX2RX_LOOPBK_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG1_RESETVAL (0x00000000u)

/* usb_reg2 */

#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_COMPDISTUNE_MASK (0x00000007u)
#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_COMPDISTUNE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_COMPDISTUNE_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_LOS_BIAS_MASK (0x38000000u)
#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_LOS_BIAS_SHIFT (0x0000001Bu)
#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_LOS_BIAS_RESETVAL (0x00000005u)

#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_OTGTUNE_MASK (0x00000070u)
#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_OTGTUNE_SHIFT (0x00000004u)
#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_OTGTUNE_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_SQRXTUNE_MASK (0x00000380u)
#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_SQRXTUNE_SHIFT (0x00000007u)
#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_SQRXTUNE_RESETVAL (0x00000003u)

#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_TXFSLSTUNE_MASK (0x00003C00u)
#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_TXFSLSTUNE_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_TXFSLSTUNE_RESETVAL (0x00000003u)

#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_TXHSXVTUNE_MASK (0x0000C000u)
#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_TXHSXVTUNE_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_TXHSXVTUNE_RESETVAL (0x00000003u)

#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_TXPREEMPAMPTUNE_MASK (0x00030000u)
#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_TXPREEMPAMPTUNE_SHIFT (0x00000010u)
#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_TXPREEMPAMPTUNE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_TXPREEMPPULSETUNE_MASK (0x00040000u)
#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_TXPREEMPPULSETUNE_SHIFT (0x00000012u)
#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_TXPREEMPPULSETUNE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_TXRESTUNE_MASK (0x00180000u)
#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_TXRESTUNE_SHIFT (0x00000013u)
#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_TXRESTUNE_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_TXRISETUNE_MASK (0x00600000u)
#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_TXRISETUNE_SHIFT (0x00000015u)
#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_TXRISETUNE_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_TXVREFTUNE_MASK (0x07800000u)
#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_TXVREFTUNE_SHIFT (0x00000017u)
#define CSL_BOOTCFG_USB_REG2_USB_PHY_PC_TXVREFTUNE_RESETVAL (0x00000008u)

#define CSL_BOOTCFG_USB_REG2_RESETVAL (0x2C28CDC4u)

/* usb_reg3 */

#define CSL_BOOTCFG_USB_REG3_USB_PHY_PC_LOS_LEVEL_MASK (0x0000001Fu)
#define CSL_BOOTCFG_USB_REG3_USB_PHY_PC_LOS_LEVEL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_USB_REG3_USB_PHY_PC_LOS_LEVEL_RESETVAL (0x00000009u)

#define CSL_BOOTCFG_USB_REG3_USB_PHY_PC_PCS_TX_DEEMPH_3P5DB_MASK (0x000007E0u)
#define CSL_BOOTCFG_USB_REG3_USB_PHY_PC_PCS_TX_DEEMPH_3P5DB_SHIFT (0x00000005u)
#define CSL_BOOTCFG_USB_REG3_USB_PHY_PC_PCS_TX_DEEMPH_3P5DB_RESETVAL (0x00000015u)

#define CSL_BOOTCFG_USB_REG3_USB_PHY_PC_PCS_TX_DEEMPH_6DB_MASK (0x007E0000u)
#define CSL_BOOTCFG_USB_REG3_USB_PHY_PC_PCS_TX_DEEMPH_6DB_SHIFT (0x00000011u)
#define CSL_BOOTCFG_USB_REG3_USB_PHY_PC_PCS_TX_DEEMPH_6DB_RESETVAL (0x00000020u)

#define CSL_BOOTCFG_USB_REG3_USB_PHY_PC_PCS_TX_SWING_FULL_MASK (0x3F800000u)
#define CSL_BOOTCFG_USB_REG3_USB_PHY_PC_PCS_TX_SWING_FULL_SHIFT (0x00000017u)
#define CSL_BOOTCFG_USB_REG3_USB_PHY_PC_PCS_TX_SWING_FULL_RESETVAL (0x00000078u)

#define CSL_BOOTCFG_USB_REG3_RESETVAL (0x3C4002A9u)

/* usb_reg4 */

#define CSL_BOOTCFG_USB_REG4_USB_CTRL_MISC_DEBUG_EN_MASK (0x00020000u)
#define CSL_BOOTCFG_USB_REG4_USB_CTRL_MISC_DEBUG_EN_SHIFT (0x00000011u)
#define CSL_BOOTCFG_USB_REG4_USB_CTRL_MISC_DEBUG_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG4_USB_PHY_COMMONONN_MASK (0x00040000u)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_COMMONONN_SHIFT (0x00000012u)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_COMMONONN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG4_USB_PHY_FSEL_MASK (0x0FC00000u)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_FSEL_SHIFT (0x00000016u)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_FSEL_RESETVAL (0x00000027u)

#define CSL_BOOTCFG_USB_REG4_USB_PHY_MPLL_REFSSC_CLK_EN_MASK (0x10000000u)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_MPLL_REFSSC_CLK_EN_SHIFT (0x0000001Cu)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_MPLL_REFSSC_CLK_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG4_USB_PHY_OTG_OTGDISABLE_MASK (0x00008000u)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_OTG_OTGDISABLE_SHIFT (0x0000000Fu)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_OTG_OTGDISABLE_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_USB_REG4_USB_PHY_OTG_VBUSVLDEXTSEL_MASK (0x00010000u)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_OTG_VBUSVLDEXTSEL_SHIFT (0x00000010u)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_OTG_VBUSVLDEXTSEL_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_USB_REG4_USB_PHY_PC_LANE0_TX_TERM_OFFSET_MASK (0x00000F80u)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_PC_LANE0_TX_TERM_OFFSET_SHIFT (0x00000007u)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_PC_LANE0_TX_TERM_OFFSET_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG4_USB_PHY_PC_TX_VBOOST_LVL_MASK (0x00007000u)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_PC_TX_VBOOST_LVL_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_PC_TX_VBOOST_LVL_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_USB_REG4_USB_PHY_REF_SSP_EN_MASK (0x20000000u)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_REF_SSP_EN_SHIFT (0x0000001Du)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_REF_SSP_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG4_USB_PHY_REF_USE_PAD_MASK (0x40000000u)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_REF_USE_PAD_SHIFT (0x0000001Eu)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_REF_USE_PAD_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_USB_REG4_USB_PHY_REFCLKSEL_MASK (0x00180000u)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_REFCLKSEL_SHIFT (0x00000013u)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_REFCLKSEL_RESETVAL (0x00000002u)

#define CSL_BOOTCFG_USB_REG4_USB_PHY_RETENABLEN_MASK (0x00200000u)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_RETENABLEN_SHIFT (0x00000015u)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_RETENABLEN_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_USB_REG4_USB_PHY_SSC_EN_MASK (0x80000000u)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_SSC_EN_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_USB_REG4_USB_PHY_SSC_EN_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_USB_REG4_RESETVAL (0xC9F1C000u)

/* usb_reg5 */

#define CSL_BOOTCFG_USB_REG5_USB_PHY_MPLL_MULTIPLIER_MASK (0x000FE000u)
#define CSL_BOOTCFG_USB_REG5_USB_PHY_MPLL_MULTIPLIER_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_USB_REG5_USB_PHY_MPLL_MULTIPLIER_RESETVAL (0x00000019u)

#define CSL_BOOTCFG_USB_REG5_USB_PHY_REF_CLKDIV2_MASK (0x00100000u)
#define CSL_BOOTCFG_USB_REG5_USB_PHY_REF_CLKDIV2_SHIFT (0x00000014u)
#define CSL_BOOTCFG_USB_REG5_USB_PHY_REF_CLKDIV2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG5_USB_PHY_SSC_RANGE_MASK (0x00000007u)
#define CSL_BOOTCFG_USB_REG5_USB_PHY_SSC_RANGE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_USB_REG5_USB_PHY_SSC_RANGE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG5_USB_PHY_SSC_REF_CLK_SEL_MASK (0x00001FF0u)
#define CSL_BOOTCFG_USB_REG5_USB_PHY_SSC_REF_CLK_SEL_SHIFT (0x00000004u)
#define CSL_BOOTCFG_USB_REG5_USB_PHY_SSC_REF_CLK_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_REG5_RESETVAL (0x00032000u)

/* usb_reg6 */

#define CSL_BOOTCFG_USB_REG6_RESETVAL (0x00000000u)

/* usb_reg7 */

#define CSL_BOOTCFG_USB_REG7_RESETVAL (0x00000000u)

/* led_core_passdone0 */

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D0_MASK (0x00000002u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D0_SHIFT (0x00000001u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D1_MASK (0x00000020u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D1_SHIFT (0x00000005u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D2_MASK (0x00000200u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D2_SHIFT (0x00000009u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D3_MASK (0x00002000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D3_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D4_MASK (0x00020000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D4_SHIFT (0x00000011u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D5_MASK (0x00200000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D5_SHIFT (0x00000015u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D6_MASK (0x02000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D6_SHIFT (0x00000019u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D7_MASK (0x20000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D7_SHIFT (0x0000001Du)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I0_MASK (0x00000004u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I0_SHIFT (0x00000002u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I1_MASK (0x00000040u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I1_SHIFT (0x00000006u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I2_MASK (0x00000400u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I2_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I3_MASK (0x00004000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I3_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I4_MASK (0x00040000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I4_SHIFT (0x00000012u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I5_MASK (0x00400000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I5_SHIFT (0x00000016u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I6_MASK (0x04000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I6_SHIFT (0x0000001Au)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I7_MASK (0x40000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I7_SHIFT (0x0000001Eu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L0_MASK (0x00000008u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L0_SHIFT (0x00000003u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L1_MASK (0x00000080u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L1_SHIFT (0x00000007u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L2_MASK (0x00000800u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L2_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L3_MASK (0x00008000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L3_SHIFT (0x0000000Fu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L4_MASK (0x00080000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L4_SHIFT (0x00000013u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L5_MASK (0x00800000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L5_SHIFT (0x00000017u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L6_MASK (0x08000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L6_SHIFT (0x0000001Bu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L7_MASK (0x80000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L7_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P0_MASK (0x00000001u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P1_MASK (0x00000010u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P1_SHIFT (0x00000004u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P2_MASK (0x00000100u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P2_SHIFT (0x00000008u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P3_MASK (0x00001000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P3_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P4_MASK (0x00010000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P4_SHIFT (0x00000010u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P5_MASK (0x00100000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P5_SHIFT (0x00000014u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P6_MASK (0x01000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P6_SHIFT (0x00000018u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P7_MASK (0x10000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P7_SHIFT (0x0000001Cu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_RESETVAL (0x00000000u)

/* led_core_passdone1 */

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D0_MASK (0x00000002u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D0_SHIFT (0x00000001u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D1_MASK (0x00000020u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D1_SHIFT (0x00000005u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D2_MASK (0x00000200u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D2_SHIFT (0x00000009u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D3_MASK (0x00002000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D3_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D4_MASK (0x00020000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D4_SHIFT (0x00000011u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D5_MASK (0x00200000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D5_SHIFT (0x00000015u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D6_MASK (0x02000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D6_SHIFT (0x00000019u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D7_MASK (0x20000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D7_SHIFT (0x0000001Du)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I0_MASK (0x00000004u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I0_SHIFT (0x00000002u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I1_MASK (0x00000040u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I1_SHIFT (0x00000006u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I2_MASK (0x00000400u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I2_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I3_MASK (0x00004000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I3_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I4_MASK (0x00040000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I4_SHIFT (0x00000012u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I5_MASK (0x00400000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I5_SHIFT (0x00000016u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I6_MASK (0x04000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I6_SHIFT (0x0000001Au)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I7_MASK (0x40000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I7_SHIFT (0x0000001Eu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L0_MASK (0x00000008u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L0_SHIFT (0x00000003u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L1_MASK (0x00000080u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L1_SHIFT (0x00000007u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L2_MASK (0x00000800u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L2_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L3_MASK (0x00008000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L3_SHIFT (0x0000000Fu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L4_MASK (0x00080000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L4_SHIFT (0x00000013u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L5_MASK (0x00800000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L5_SHIFT (0x00000017u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L6_MASK (0x08000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L6_SHIFT (0x0000001Bu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L7_MASK (0x80000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L7_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P0_MASK (0x00000001u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P1_MASK (0x00000010u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P1_SHIFT (0x00000004u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P2_MASK (0x00000100u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P2_SHIFT (0x00000008u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P3_MASK (0x00001000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P3_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P4_MASK (0x00010000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P4_SHIFT (0x00000010u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P5_MASK (0x00100000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P5_SHIFT (0x00000014u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P6_MASK (0x01000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P6_SHIFT (0x00000018u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P7_MASK (0x10000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P7_SHIFT (0x0000001Cu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_RESETVAL (0x00000000u)

/* led_arm_bootaddr */

#define CSL_BOOTCFG_LED_ARM_BOOTADDR_LED_ARM_BOOTADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_LED_ARM_BOOTADDR_LED_ARM_BOOTADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_LED_ARM_BOOTADDR_LED_ARM_BOOTADDR_RESETVAL (0x000000C4u)

#define CSL_BOOTCFG_LED_ARM_BOOTADDR_LED_ARM_SELECT_MASK (0x00000001u)
#define CSL_BOOTCFG_LED_ARM_BOOTADDR_LED_ARM_SELECT_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LED_ARM_BOOTADDR_LED_ARM_SELECT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_ARM_BOOTADDR_RESETVAL (0x0000C400u)

/* led_gpio_clr */


#define CSL_BOOTCFG_LED_GPIO_CLR_RESETVAL (0x00000000u)

/* led_gpio_clr1 */

#define CSL_BOOTCFG_LED_GPIO_CLR1_RESETVAL (0x00000000u)

/* led_gpio */


#define CSL_BOOTCFG_LED_GPIO_RESETVAL (0x00000000u)

/* led_gpio1 */

#define CSL_BOOTCFG_LED_GPIO1_RESETVAL (0x00000000u)

/* led_plllock0 */

#define CSL_BOOTCFG_LED_PLLLOCK0_PLLLOCK_MASK (0x00000001u)
#define CSL_BOOTCFG_LED_PLLLOCK0_PLLLOCK_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LED_PLLLOCK0_PLLLOCK_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK0_STICKY_EN_LOCK_MASK (0x00000002u)
#define CSL_BOOTCFG_LED_PLLLOCK0_STICKY_EN_LOCK_SHIFT (0x00000001u)
#define CSL_BOOTCFG_LED_PLLLOCK0_STICKY_EN_LOCK_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK0_RESETVAL (0x00000000u)

/* led_plllock1 */

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE0_CODE_LOADED_MASK (0x00000001u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE0_CODE_LOADED_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE0_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE0_EXE_OK_MASK (0x00000002u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE0_EXE_OK_SHIFT (0x00000001u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE0_EXE_OK_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE1_CODE_LOADED_MASK (0x00000004u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE1_CODE_LOADED_SHIFT (0x00000002u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE1_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE1_EXE_OK_MASK (0x00000008u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE1_EXE_OK_SHIFT (0x00000003u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE1_EXE_OK_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE2_CODE_LOADED_MASK (0x00000010u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE2_CODE_LOADED_SHIFT (0x00000004u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE2_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE2_EXE_OK_MASK (0x00000020u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE2_EXE_OK_SHIFT (0x00000005u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE2_EXE_OK_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE3_CODE_LOADED_MASK (0x00000040u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE3_CODE_LOADED_SHIFT (0x00000006u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE3_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE3_EXE_OK_MASK (0x00000080u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE3_EXE_OK_SHIFT (0x00000007u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE3_EXE_OK_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE4_CODE_LOADED_MASK (0x00000100u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE4_CODE_LOADED_SHIFT (0x00000008u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE4_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE4_EXE_OK_MASK (0x00000200u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE4_EXE_OK_SHIFT (0x00000009u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE4_EXE_OK_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE5_CODE_LOADED_MASK (0x00000400u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE5_CODE_LOADED_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE5_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE5_EXE_OK_MASK (0x00000800u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE5_EXE_OK_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE5_EXE_OK_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE6_CODE_LOADED_MASK (0x00001000u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE6_CODE_LOADED_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE6_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE6_EXE_OK_MASK (0x00002000u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE6_EXE_OK_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE6_EXE_OK_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE7_CODE_LOADED_MASK (0x00004000u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE7_CODE_LOADED_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE7_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE7_EXE_OK_MASK (0x00008000u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE7_EXE_OK_SHIFT (0x0000000Fu)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE7_EXE_OK_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE_GENERAL_MASK (0x1FFF0000u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE_GENERAL_SHIFT (0x00000010u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE_GENERAL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE_SUSP_CTL_MASK (0x80000000u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE_SUSP_CTL_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE_SUSP_CTL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_RESETVAL (0x0000AAAAu)

/* led_chip_passdone */

#define CSL_BOOTCFG_LED_CHIP_PASSDONE_CHIP_DONE_MASK (0x00000002u)
#define CSL_BOOTCFG_LED_CHIP_PASSDONE_CHIP_DONE_SHIFT (0x00000001u)
#define CSL_BOOTCFG_LED_CHIP_PASSDONE_CHIP_DONE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CHIP_PASSDONE_CHIP_PASS_MASK (0x00000001u)
#define CSL_BOOTCFG_LED_CHIP_PASSDONE_CHIP_PASS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LED_CHIP_PASSDONE_CHIP_PASS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CHIP_PASSDONE_LED_CHIP_PASSDONE_RSVD_MASK (0xFFFFFFFCu)
#define CSL_BOOTCFG_LED_CHIP_PASSDONE_LED_CHIP_PASSDONE_RSVD_SHIFT (0x00000002u)
#define CSL_BOOTCFG_LED_CHIP_PASSDONE_LED_CHIP_PASSDONE_RSVD_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CHIP_PASSDONE_RESETVAL (0x00000000u)

/* tdiode */

#define CSL_BOOTCFG_TDIODE_TDIODE_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_TDIODE_TDIODE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_TDIODE_TDIODE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TDIODE_RESETVAL  (0x00000000u)

/* margin */

#define CSL_BOOTCFG_MARGIN0_BTCFG_MARGIN_EN_MASK (0x80000000u)
#define CSL_BOOTCFG_MARGIN0_BTCFG_MARGIN_EN_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_MARGIN0_BTCFG_MARGIN_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MARGIN0_DFTWRITE0_MASK (0x00FFFFFFu)
#define CSL_BOOTCFG_MARGIN0_DFTWRITE0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_MARGIN0_DFTWRITE0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MARGIN0_RESETVAL  (0x00000000u)

/* margin1 */

#define CSL_BOOTCFG_MARGIN1_DFTWRITE1_MASK (0x00FFFFFFu)
#define CSL_BOOTCFG_MARGIN1_DFTWRITE1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_MARGIN1_DFTWRITE1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MARGIN1_RESETVAL  (0x00000000u)

/* margin2 */

#define CSL_BOOTCFG_MARGIN2_DFTREAD0_MASK (0x00FFFFFFu)
#define CSL_BOOTCFG_MARGIN2_DFTREAD0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_MARGIN2_DFTREAD0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MARGIN2_RESETVAL  (0x00000000u)

/* efuse_secrom_chksum0 */

#define CSL_BOOTCFG_EFUSE_SECROM_CHKSUM0_EFUSE_SECROM_CHKSUM0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE_SECROM_CHKSUM0_EFUSE_SECROM_CHKSUM0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE_SECROM_CHKSUM0_EFUSE_SECROM_CHKSUM0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE_SECROM_CHKSUM0_RESETVAL (0x00000000u)

/* efuse_secrom_chksum1 */

#define CSL_BOOTCFG_EFUSE_SECROM_CHKSUM1_EFUSE_SECROM_CHKSUM1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE_SECROM_CHKSUM1_EFUSE_SECROM_CHKSUM1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE_SECROM_CHKSUM1_EFUSE_SECROM_CHKSUM1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE_SECROM_CHKSUM1_RESETVAL (0x00000000u)

/* efuse_secrom_chksum2 */

#define CSL_BOOTCFG_EFUSE_SECROM_CHKSUM2_RESETVAL (0x00000000u)

/* efuse_secrom_chksum3 */

#define CSL_BOOTCFG_EFUSE_SECROM_CHKSUM3_RESETVAL (0x00000000u)

/* int_spare0 */

#define CSL_BOOTCFG_INT_SPARE0_EFC_AUTOLOAD_DONE_MASK (0x000000F0u)
#define CSL_BOOTCFG_INT_SPARE0_EFC_AUTOLOAD_DONE_SHIFT (0x00000004u)
#define CSL_BOOTCFG_INT_SPARE0_EFC_AUTOLOAD_DONE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_SPARE0_EFC_AUTOLOAD_ERR_MASK (0x00000F00u)
#define CSL_BOOTCFG_INT_SPARE0_EFC_AUTOLOAD_ERR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_INT_SPARE0_EFC_AUTOLOAD_ERR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_SPARE0_EFC_ERR_MASK (0x00001000u)
#define CSL_BOOTCFG_INT_SPARE0_EFC_ERR_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_INT_SPARE0_EFC_ERR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_SPARE0_EFC_INFO_MASK (0x00002000u)
#define CSL_BOOTCFG_INT_SPARE0_EFC_INFO_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_INT_SPARE0_EFC_INFO_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_SPARE0_INT_SPARE0_MASK (0xFFFFC000u)
#define CSL_BOOTCFG_INT_SPARE0_INT_SPARE0_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_INT_SPARE0_INT_SPARE0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_SPARE0_SERDES_TEST_EN_MASK (0x00000008u)
#define CSL_BOOTCFG_INT_SPARE0_SERDES_TEST_EN_SHIFT (0x00000003u)
#define CSL_BOOTCFG_INT_SPARE0_SERDES_TEST_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_SPARE0_SERDES_TEST_SELECT_MASK (0x00000007u)
#define CSL_BOOTCFG_INT_SPARE0_SERDES_TEST_SELECT_SHIFT (0x00000000u)
#define CSL_BOOTCFG_INT_SPARE0_SERDES_TEST_SELECT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_SPARE0_RESETVAL (0x00000000u)

/* int_spare1 */

#define CSL_BOOTCFG_INT_SPARE1_INT_SPARE1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_INT_SPARE1_INT_SPARE1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_INT_SPARE1_INT_SPARE1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_SPARE1_RESETVAL (0x00000000u)

/* led_misc_ctl */

#define CSL_BOOTCFG_LED_MISC_CTL_RESETVAL (0x00000000u)

/* chip_misc1 */

#define CSL_BOOTCFG_CHIP_MISC1_CHIP_MISC_GEM_EMIF4F_PSC_LOCK_N_MASK (0x00000800u)
#define CSL_BOOTCFG_CHIP_MISC1_CHIP_MISC_GEM_EMIF4F_PSC_LOCK_N_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_CHIP_MISC1_CHIP_MISC_GEM_EMIF4F_PSC_LOCK_N_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC1_CHIP_MISC_GEM_L2ACS_LAT_MASK (0x00000780u)
#define CSL_BOOTCFG_CHIP_MISC1_CHIP_MISC_GEM_L2ACS_LAT_SHIFT (0x00000007u)
#define CSL_BOOTCFG_CHIP_MISC1_CHIP_MISC_GEM_L2ACS_LAT_RESETVAL (0x00000003u)

#define CSL_BOOTCFG_CHIP_MISC1_CHIP_MISC_GEM_L2RDLAT_MASK (0x00000078u)
#define CSL_BOOTCFG_CHIP_MISC1_CHIP_MISC_GEM_L2RDLAT_SHIFT (0x00000003u)
#define CSL_BOOTCFG_CHIP_MISC1_CHIP_MISC_GEM_L2RDLAT_RESETVAL (0x00000003u)

#define CSL_BOOTCFG_CHIP_MISC1_IO_TRACE_SEL_MASK (0x00004000u)
#define CSL_BOOTCFG_CHIP_MISC1_IO_TRACE_SEL_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_CHIP_MISC1_IO_TRACE_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC1_TETRIS_PBIST_ENABLE_MASK (0x00001000u)
#define CSL_BOOTCFG_CHIP_MISC1_TETRIS_PBIST_ENABLE_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_CHIP_MISC1_TETRIS_PBIST_ENABLE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC1_TETRIS_PLL_ENABLE_MASK (0x00002000u)
#define CSL_BOOTCFG_CHIP_MISC1_TETRIS_PLL_ENABLE_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_CHIP_MISC1_TETRIS_PLL_ENABLE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC1_RESETVAL (0x00000198u)

/* obsclk_ctl */

#define CSL_BOOTCFG_OBSCLK_CTL_CORE_PLL_OBSCLK_EN_MASK (0x00000002u)
#define CSL_BOOTCFG_OBSCLK_CTL_CORE_PLL_OBSCLK_EN_SHIFT (0x00000001u)
#define CSL_BOOTCFG_OBSCLK_CTL_CORE_PLL_OBSCLK_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_OBSCLK_CTL_CORE_PLL_OBSCLK_SEL_MASK (0x00000001u)
#define CSL_BOOTCFG_OBSCLK_CTL_CORE_PLL_OBSCLK_SEL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_OBSCLK_CTL_CORE_PLL_OBSCLK_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_OBSCLK_CTL_DDR3A_PLL_OBSCLK_EN_MASK (0x00000008u)
#define CSL_BOOTCFG_OBSCLK_CTL_DDR3A_PLL_OBSCLK_EN_SHIFT (0x00000003u)
#define CSL_BOOTCFG_OBSCLK_CTL_DDR3A_PLL_OBSCLK_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_OBSCLK_CTL_DDR3A_PLL_OBSCLK_SEL_MASK (0x00000004u)
#define CSL_BOOTCFG_OBSCLK_CTL_DDR3A_PLL_OBSCLK_SEL_SHIFT (0x00000002u)
#define CSL_BOOTCFG_OBSCLK_CTL_DDR3A_PLL_OBSCLK_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_OBSCLK_CTL_PA_PLL_OBSCLK_EN_MASK (0x00000020u)
#define CSL_BOOTCFG_OBSCLK_CTL_PA_PLL_OBSCLK_EN_SHIFT (0x00000005u)
#define CSL_BOOTCFG_OBSCLK_CTL_PA_PLL_OBSCLK_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_OBSCLK_CTL_PA_PLL_OBSCLK_SEL_MASK (0x00000010u)
#define CSL_BOOTCFG_OBSCLK_CTL_PA_PLL_OBSCLK_SEL_SHIFT (0x00000004u)
#define CSL_BOOTCFG_OBSCLK_CTL_PA_PLL_OBSCLK_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_OBSCLK_CTL_DDR3B_PLL_OBSCLK_EN_MASK (0x00000040u)
#define CSL_BOOTCFG_OBSCLK_CTL_DDR3B_PLL_OBSCLK_EN_SHIFT (0x00000006u)
#define CSL_BOOTCFG_OBSCLK_CTL_DDR3B_PLL_OBSCLK_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_OBSCLK_CTL_RESETVAL (0x00000000u)

/* chip_misc2 */

#define CSL_BOOTCFG_CHIP_MISC2_RXCLK0SEL_MASK (0x00000007u)
#define CSL_BOOTCFG_CHIP_MISC2_RXCLK0SEL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_CHIP_MISC2_RXCLK0SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC2_RXCLK1SEL_MASK (0x00000038u)
#define CSL_BOOTCFG_CHIP_MISC2_RXCLK1SEL_SHIFT (0x00000003u)
#define CSL_BOOTCFG_CHIP_MISC2_RXCLK1SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC2_RESETVAL (0x00000000u)

/* chip_misc3 */

#define CSL_BOOTCFG_CHIP_MISC3_DBG_PLLLOCK_SELECT_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_CHIP_MISC3_DBG_PLLLOCK_SELECT_SHIFT (0x00000000u)
#define CSL_BOOTCFG_CHIP_MISC3_DBG_PLLLOCK_SELECT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC3_RESETVAL (0x00000000u)

/* efuse_rsvd0 */

#define CSL_BOOTCFG_EFUSE_RSVD0_EFUSE_RSVD0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE_RSVD0_EFUSE_RSVD0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE_RSVD0_EFUSE_RSVD0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE_RSVD0_RESETVAL (0x00000000u)

/* efuse_rsvd1 */

#define CSL_BOOTCFG_EFUSE_RSVD1_EFUSE_RSVD1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE_RSVD1_EFUSE_RSVD1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE_RSVD1_EFUSE_RSVD1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE_RSVD1_RESETVAL (0x00000000u)

/* efuse_rsvd2 */

#define CSL_BOOTCFG_EFUSE_RSVD2_EFUSE_RSVD2_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE_RSVD2_EFUSE_RSVD2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE_RSVD2_EFUSE_RSVD2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE_RSVD2_RESETVAL (0x00000000u)

/* efuse_rsvd3 */

#define CSL_BOOTCFG_EFUSE_RSVD3_RESETVAL (0x00000000u)

/* pwrswtch_wkup_mode0_0 */

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_0_PWRSWTCH_WKUP_MODE0_0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_0_PWRSWTCH_WKUP_MODE0_0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_0_PWRSWTCH_WKUP_MODE0_0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_0_RESETVAL (0x00000000u)

/* pwrswtch_wkup_mode0_1 */

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_1_PWRSWTCH_WKUP_MODE0_1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_1_PWRSWTCH_WKUP_MODE0_1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_1_PWRSWTCH_WKUP_MODE0_1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_1_RESETVAL (0x00000000u)

/* pwrswtch_wkup_mode1_0 */

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_0_PWRSWTCH_WKUP_MODE1_0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_0_PWRSWTCH_WKUP_MODE1_0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_0_PWRSWTCH_WKUP_MODE1_0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_0_RESETVAL (0x00000000u)

/* pwrswtch_wkup_mode1_1 */

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_1_PWRSWTCH_WKUP_MODE1_1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_1_PWRSWTCH_WKUP_MODE1_1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_1_PWRSWTCH_WKUP_MODE1_1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_1_RESETVAL (0x00000000u)

/* end_point */

#define CSL_BOOTCFG_END_POINT_RESETVAL (0x00000000u)


#ifdef __cplusplus
}
#endif

#endif
